Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 44 (10x10) 8-Bit 20 MHz I/O number 32

Features

• High-performance, Low-power AVR

8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 16/32/64/128K Bytes of In-System Self-programmable Flash program memory

– 512B/1K/2K/4K Bytes EEPROM

– 1/2/4/16K Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

• Operating Voltages

– 1.8 - 5.5V

• Speed Grades

– 0 - 4 MHz @ 1.8 - 5.5V

– 0 - 10 MHz @ 2.7 - 5.5V

– 0 - 20 MHz @ 4.5 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C

– Active: 0.4 mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32 kHz RTC)

Note: 1. See ”Data Retention” on page 9 for details.

8-bit

Microcontroller

with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164A

ATmega164PA

ATmega324A

ATmega324PA

ATmega644A

ATmega644PA

ATmega1284

ATmega1284P

8272A–AVR–01/10

Summary of content (581 pages)

PAGE 1
Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 16/32/64/128K Bytes of In-System Self-programmable Flash program memory – 512B/1K/2K/4K Bytes EEPROM – 1/2/4/16K Bytes Internal SRAM – Write/Erase Cycles: 10
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1. Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 1-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1.2 Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1-2. DRQFN - Pinout Top view Bottom view A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A18 B1 B15 A17 B2 B14 B3 B4 A2 A3 A4 Table 1-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1-3. VFBGA - Pinout Top view 1 2 3 4 5 Bottom view 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 1-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 2. Overview The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA7..0 PB7..
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16/32/64/128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K/4K bytes EEPROM, 1/2/4/16K/ bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 2.3.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset Characteristics” on page 335. Shorter pulses are not guaranteed to generate a reset. 2.3.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.9 XTAL2 Output from the inverting Oscillator amplifier. 2.3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 3. Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 6. AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 6-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 6.3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 6.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 6.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3. Figure 6-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 6.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value Note: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0/0(1) 0/1(1) 1/0(1) 0 0 1 1 1 1 1 1 1 1 1.
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4A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 6-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 6.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes five clock cycles.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 7. AVR Memories 7.1 Overview This section describes the different memories in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 7-1. Program Memory Map Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF/0x3FFF/0x7FFF/0xFFFF 7.3 SRAM Data Memory Figure 7-2 shows how the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P SRAM Memory is organized. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 13. Figure 7-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 7.4 EEPROM Data Memory The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 512B/1K/2K/4K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 7.5 I/O Memory The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is shown in ”Register Summary” on page 551. All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 7.6 7.6.
PAGE 25
164A/164PA/324A/324PA/644A/644PA/1284/1284P operations. The Programming times for the different modes are shown in Table 7-1 on page 25. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 7-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM.
PAGE 27
164A/164PA/324A/324PA/644A/644PA/1284/1284P The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 7.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 7.6.5 7 5 4 3 2 1 0 MSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB 5 4 3 2 1 GPIOR2 GPIOR1 – General Purpose I/O Register 1 Bit 7.6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 43. The clock systems are detailed below. Figure 8-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 8.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal.
PAGE 32
164A/164PA/324A/324PA/644A/644PA/1284/1284P selectable delays are shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 342. Table 8-2. Number of Watchdog Oscillator Cycles Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 0 ms 0 ms 0 4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.3 Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the ”Full Swing Crystal Oscillator” on page 34. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Crystal Oscillator, BOD enabled 16K CK 14CK 1 01 Crystal Oscillator, fast rising power 16K CK 14CK + 4.1 ms 1 10 Crystal Oscillator, slowly rising power 16K CK 14CK + 65 ms 1 11 Oscillator Source / Power Conditions Notes: 8.4 1.
PAGE 35
164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 8-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast rising power 1K CK 14CK + 4.1 ms(2) 0 11 Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms(2) 1 00 Crystal Oscillator, BOD enabled 16K CK 14CK 1 01 Crystal Oscillator, fast rising power 16K CK 14CK + 4.
PAGE 36
164A/164PA/324A/324PA/644A/644PA/1284/1284P Ce - is optional external capacitors as described in Figure 8-2 on page 32 Ci - is is the pin capacitance in Table 8-8 on page 35 CL - is the load capacitance for a 32.768 kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one TOSC pin. Crystals specifying load capacitance (CL) higher than the ones given in the Table 8-8 on page 35, require external capacitors applied as described in Figure 8-2 on page 32. Figure 8-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See Table 27-10 on page 334 and ”Internal Oscillator Speed” on page 387 and page 439 for more details. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 40 for more details.
PAGE 38
164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.7 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “0011” as shown in Table 8-12. Table 8-12. Note: 128 kHz Internal Oscillator Operating Modes(2) Nominal Frequency CKSEL3..0 128 kHz 0011 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 8-14. Table 8-15. Crystal Oscillator Clock Frequency Nominal Frequency CKSEL3..0 0 - 20 MHz 0000 Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.11 System Clock Prescaler The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has a system clock prescaler, and the system clock can be divided by setting the ”CLKPR – Clock Prescale Register” on page 41. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.12 8.12.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9. Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.3 BOD Disable(1) When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 26-3 on page 296, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page 43. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.6 Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2wire Serial Interface, and the Watchdog continue operating (if enabled).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.10 Power Reduction Register The Power Reduction Register(PRR), see ”PRR – Power Reduction Register” on page 49, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.11.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Interrupts” on page 62 for details on how to configure the Watchdog Timer. 9.11.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.12 9.12.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2. Table 9-2.
PAGE 49
164A/164PA/324A/324PA/644A/644PA/1284/1284P 9.12.2 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the ATmega164PA/324PA/644PA/1284P. • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1 on page 43.
PAGE 50
164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
PAGE 52
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 10-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 10.1.2 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
PAGE 53
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 10-2. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 10-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 10.1.3 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 335) will generate a reset, even if the clock is not running.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 10.1.4 Brown-out Detection ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
PAGE 55
164A/164PA/324A/324PA/644A/644PA/1284/1284P 10.2 Internal Voltage Reference ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”System and Reset Characteristics” on page 335.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 10.3 10.3.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 10.3.2 Overview ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 10.4 10.4.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 10.4.2 WDTCSR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 10-2 on page 61. . Table 10-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 11. Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 16. 11.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 11-1. Vector No.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 11-1. Vector No. Reset and Interrupt Vectors (Continued) Program Address(2) Source Interrupt Definition 28 $0036 SPM_READY Store Program Memory Ready 29 $0038 USART1_RX USART1 Rx Complete 30 $003A USART1_UDRE USART1 Data Register Empty 31 $003C USART1_TX USART1 Tx Complete Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Memory Programming” on page 295. 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C ; 0x003E RESET: jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp TIM0_COMPB TIM0_OVF SPI_STC USART0_RXC USART0_UDRE USART0_TXC ANA_COMP ADC EE_RDY TWI SPM_RDY USART1_RXC USART1_UDRE USART1_TXC ; ; ; ; ; ; ; ; ; ; ; ; ; ; ldi r16, high(RAMEND) SPH,r16 ; Main program start 0x003F out 0x0040 ldi 0x0041 0x0042 0x0043 ... out sei ... ...
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 0x00004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x00036 jmp SPM_RDY ; SPM Ready Handler ; .
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 11.3 11.3.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the ATmega164PA/324PA/644PA/1284P. • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 12. External Interrupts 12.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 12.2.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – PCIE3 PCIE2 PCIE1 PCIE0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT31..24 pin will cause an interrupt.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 12.2.9 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 13.2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 13-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 on page 74 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 13-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 13-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.3.1 Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 13-3. Table 13-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 13-4 on page 82 and Table 13-5 on page 82 relates the alternate functions of Port A to the overriding signals shown in Figure 13-5 on page 79. Table 13-4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Table 13-6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • MOSI/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.3.3 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-9. Table 13-9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • TMS/PCINT19 – Port C, Bit 3 TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt source. • TCK/PCINT18 – Port C, Bit 2 TCK, JTAG Test Clock. PCINT18, Pin Change Interrupt source 18: The PC2 pin can serve as an external interrupt source. • SDA/PCINT17 – Port C, Bit 1 SDA, 2-wire Serial Bus Data Input/Output Line.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 13.3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The alternate pin configuration is as follows: • OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDD7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. PCINT31, Pin Change Interrupt Source 31:The PD7 pin can serve as an external interrupt source.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • INT0/RXD1/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 13-14.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Register Description 13.3.5 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the ATmega164PA/324PA/644PA/1284P.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 13.3.12 PORTC – Port C Data Register Bit 13.3.13 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 14. 8-bit Timer/Counter0 with PWM 14.1 Features • • • • • • • 14.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 14-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 14.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 14-2 on page 105.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 14-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 14-6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 14-4 on page 106). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 14-10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 14.9 14.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 14-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 14-7 on page 107 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 14-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 14.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 14.9.5 OCR0B – Output Compare Register B Bit 7 6 5 0x28 (0x48) 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 14.9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 15. 16-bit Timer/Counter1 with PWM 15.1 Features • • • • • • • • • • • 15.2 True 16-bit Design (i.e.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 15-1. 16-bit Timer/Counter Block Diagram(Note:) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 15.2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P See Section “15.7” on page 121.. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See Section “21.” on page 238.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 114. 15.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 15.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 15.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 133.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 15-6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P rect and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P OCRnx Registers are written. As the third period shown in Figure 15-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 15.11 Register Description 15.11.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 15-3 on page 134 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 15-3. Compare Output Mode, Fast PWM(1) COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Waveform Generation Mode Bit Description(1) Table 15-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 15.11.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 15.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See Section “10.3” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set. 15.11.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 16.1 Features • • • • • • • 16.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surrounding environment. Figure 16-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page 145). Figure 15-10 on page 131 shows a block diagram of the Output Compare unit. Figure 16-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on page 154. 16.6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The timing diagram for the CTC mode is shown in Table 16-5 on page 146. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 16-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-6 on page 147.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 16.7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 16-4 on page 155). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 16-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 16-9 on page 150 shows the same timing data, but with the prescaler enabled. Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 16-10 on page 150 shows the setting of OCF2A in all modes except CTC mode. Figure 16-10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 16-11 on page 151 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 16.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.10 Timer/Counter Prescaler Figure 16-12. Prescaler for Timer/Counter2 PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.11 Register Description 16.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 16-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 16-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 16-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 16-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: Description 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 16-9. Clock Select Bit Description CS22 CS21 CS20 Description 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 16.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Initial Value 0 0 0 0 0 0 0 0 • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.11.9 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 - TSM: Timer/Counter Synchronization mode Writing the TSM bit to one, activates the Timer/Counter Synchronization mode.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 17. SPI – Serial Peripheral Interface 17.1 Features • • • • • • • • 17.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 17-1. SPI Block Diagram(1) SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: 1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 83 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
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A/164PA/324A/324PA/644A/644PA/1284/1284P Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 17-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 17.3 17.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 17-2. SPI Modes SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Figure 17-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 17.5 17.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 17-5. 17.5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 17.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 18. USART 18.1 Features • • • • • • • • • • • • 18.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 18-2 shows a block diagram of the clock generation logic. Figure 18-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 18-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK < ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 18.4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 18-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 18.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P transmission is used, the Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 18.8.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 18.8.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 18-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 18-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 18.11 Register Description 18.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 18-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 18-8. Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge UCPOLn 18.11.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 18.12 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 18-9 to Table 18-12. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 19. USART in SPI Mode 19.1 Features • • • • • • • • 19.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 19.4 BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 19-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. 16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. 19.5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 19.6.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 19.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 19.8 Register Description The following section describes the registers used for SPI operation using the USART. 19.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 190. 19.8.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 - UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Frame Formats section page 4 for details.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20. 2-wire Serial Interface 20.1 Features • • • • • • • • • • 20.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The Power Reduction TWI bit, PRTWI bit in ”PRR – Power Reduction Register” on page 49 must be written to zero to enable the 2-wire Serial Interface. 20.2.2 Electrical Interconnection As depicted in Figure 20-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 20-3. START, REPEATED START and STOP conditions SDA SCL START 20.3.3 STOP REPEATED START START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Figure 20-8. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 20-9. All registers drawn in a thick line are accessible through the AVR data bus. Figure 20-9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR) ⋅ 4 • TWBR = Value of the TWI Bit Rate Register. • TWPS = Value of the prescaler bits in the TWI Status Register. Note: 20.5.3 Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See 2-wire Serial Bus Requirements in Table 27-16 on page 337 for value of pull-up resistor.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. 20.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-11. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........
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164A/164PA/324A/324PA/644A/644PA/1284/1284P After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 20-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-12.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........
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164A/164PA/324A/324PA/644A/644PA/1284/1284P the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 20-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-14.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 20-4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 20-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 20.7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. • Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. 20.9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7:0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. 20.9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 20-22. TWI Address Match Logic, Block Diagram TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 • Bit 0 – Res: Reserved Bit This bit is reserved and will always read as zero.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 21. AC - Analog Comparator 21.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 21-1. 21.3 21.3.1 Analog Comparator Mulitiplexed Input ACME ADEN MUX2..
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 22. ADC - Analog-to-digital Converter 22.1 Features • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels Differential mode with selectable gain at 1x, 10x or 200x Optional Left adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.56V or 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 22-1. Analog-to-digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADSC ADATE TRIGGER SELECT AREF ADC[9:0] ADIF ADPS[2:0] ADEN DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 22-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See ”Differential Gain Channels” on page 247 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 22-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 2 1 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update Figure 22-6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 22-1. ADC Conversion Time Condition Conversion Time (Cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Auto Triggered conversions Normal conversions, differential 22.5.1 Sample & Hold (Cycles from Start of Conversion) Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 22-8. Analog Input Circuitry IIH ADCn 1..
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 22.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 22.7.4 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 22-10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 22-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 22-13.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 22.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 22-3 on page 256 and Table 22-4 on page 257).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 22-14. Differential Measurement Range Output Code 0x1FF 0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts) 0x200 Table 22-2. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999 VREF/GAIN 0x1FF 511 VADCm + 0.998 VREF/GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 22.9 22.9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 22-4. Input Channel and Gain Selections MUX4..
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 22.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 22-5. 22.9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 7, 5:3 – Res: Reserved Bits These bits are reserved for future use in the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For ensuring compability with future devices, these bits must be written zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 23. JTAG Interface and On-chip Debug System 23.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 23-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 23.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 265. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24. IEEE 1149.1 (JTAG) Boundary-scan 24.1 Features • • • • • 24.2 JTAG (IEEE std. 1149.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 24.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 24-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 24.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 270 for a complete description. 24.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 24.4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a simple digital port pin as described in the section ”I/O-Ports” on page 73. The Boundary-scan details from Figure 24-3 replaces the dashed box in Figure 24-4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 24-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q D RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 24.5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24.6 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan Order Table 24-1 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port K is scanned in the opposite bit order of the other ports.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 24-1. ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan Order (Continued) Bit Number Signal Name 39 PD0.Data 38 PD0.Control 37 PD1.Data 36 PD1.Control 35 PD2.Data 34 PD2.Control 33 PD3.Data 32 PD3.Control 31 PD4.Data 30 PD4.Control 29 PD5.Data 28 PD5.Control 27 PD6.Data 26 PD6.Control 25 PD7.Data 24 PD7.Control 23 PC0.Data 22 PC0.Control 21 PC1.Data 20 PC1.Control 19 PC6.Data 18 PC6.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 24-1. 24.7 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan Order (Continued) Bit Number Signal Name 14 PA7.Control 13 PA6.Data 12 PA6.Control 11 PA5.Data 10 PA5.Control 9 PA4.Data 8 PA4.Control 7 PA3.Data 6 PA3.Control 5 PA2.Data 4 PA2.Control 3 PA1.Data 2 PA1.Control 1 PA0.Data 0 PA0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24.8 24.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the ATmega164PA/324PA/644PA/1284P.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25. Boot Loader Support – Read-While-Write Self-Programming 25.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 25.2 1. A page is a section in the Flash consisting of several bytes (see Table 26-7 on page 298) used during programming.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 25-1. Read-While-Write vs.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 25-2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 25-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 26-7 on page 298), the Program Counter can be treated as having two different sections.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • Page Write to the RWW section: The NRWW section can be read during the Page Write.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 25.8.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Table 25-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.13 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.14 ATmega164A/ATmega164PA Boot Loader Parameters In Table 25-7 through Table 25-9, the parameters used in the description of the Self-Programming are given. Table 25-7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.15 ATmega324A/ATmega324PA Boot Loader Parameters In Table 25-10 through Table 25-12, the parameters used in the description of the Self-Programming are given. Table 25-10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.16 ATmega644A/ATmega644PA Boot Loader Parameters In Table 25-13 through Table 25-15, the parameters used in the description of the Self-Programming are given. Table 25-13.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.8.17 ATmega1284/ATmega1284P Boot Loader Parameters In Table 25-16 through Table 25-18, the parameters used in the description of the Self-Programming are given. Table 25-16.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 25.9 25.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26. Memory Programming 26.1 Program And Data Memory Lock Bits The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 26-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 26-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Lock Bit Protection Modes(1)(2) (Continued) Table 26-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 26.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-8. No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB ATmega164A/ATmega164PA 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 ATmega324A/ATmega324PA 1 Kbytes 4 bytes EEA[1:0] 256 EEA[9:2] 9 ATmega644A/ATmega644PA 2 Kbytes 8 bytes EEA[2:0] 256 EEA[10:2] 10 ATmega1284/ATmega1284P 4 Kbytes 8 bytes EEA[2:0] 512 EEA[11:3] 11 26.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1. XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-13. Command Byte Bit Encoding Command Byte 26.7 26.7.1 Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 26.7.4 Programming the Flash The Flash is organized in pages, see Table 26-7 on page 298.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “01”. This selects the address high byte. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Load Address Extended High byte (Address bits 23..16) 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “10”. This selects the address extended high byte. 3. Set DATA = Address extended high byte (0x00 - 0xFF).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-3. Programming the Flash Waveforms(1) F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 26.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 26-8 on page 299.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 26.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.7.15 Parallel Programming Characteristics Table 26-14. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 26-8.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 26-15 on page 310, the pin mapping for serial programming is listed.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.8.2 Serial Programming Algorithm When writing serial data to the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the rising edge of SCK. When reading data from the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the falling edge of SCK. See Figure 26-12 for timing details.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-16. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 26.9 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Serial Programming Instruction set Table 26-17 on page 312 and Figure 26-11 on page 313 describes the Instruction set. Table 26-17.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address. Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.9.1 Serial Programming Characteristics For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page 336. Figure 26-12. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 26.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 26.10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.10.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.10.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-15.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-18. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 26-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 26-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 0 1 Update-IR 0 1 0 26.10.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 26-17.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 26.10.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 26-14 on page 308). 26.10.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 324. 1. Enter JTAG instruction PROG_COMMANDS. 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c and 3d. PCWORD (refer to Table 26-7 on page 298) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 26-14 on page 308). 26.10.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27. Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 27-1. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.1.1 ATmega164A DC Characteristics Table 27-2. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode(3) Power-down mode(3) Notes: Max. Units Active 1 MHz, VCC = 2V 0.3 0.55 mA Active 4 MHz, VCC = 3V 1.4 3.5 mA Active 8 MHz, VCC = 5V 4.8 12 mA Idle 1 MHz, VCC = 2V 0.07 0.5 mA Idle 4 MHz, VCC = 3V 0.25 1.5 mA Idle 8 MHz, VCC = 5V 1.0 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.1.3 ATmega324A DC Characteristics Table 27-4. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode(3) Power-down mode(3) Notes: Max. Units Active 1 MHz, VCC = 2V 0.3 0.55 mA Active 4 MHz, VCC = 3V 1.5 3.5 mA Active 8 MHz, VCC = 5V 5.2 12 mA Idle 1 MHz, VCC = 2V 0.06 0.5 mA Idle 4 MHz, VCC = 3V 0.35 1.5 mA Idle 8 MHz, VCC = 5V 1.3 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.1.5 ATmega644A DC Characteristics Table 27-6. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode(3) Power-down mode(3) Notes: Max. Units Active 1 MHz, VCC = 2V 0.38 0.5 mA Active 4 MHz, VCC = 3V 1.8 2.7 mA Active 8 MHz, VCC = 5V 5.6 9.0 mA Idle 1 MHz, VCC = 2V 0.06 0.15 mA Idle 4 MHz, VCC = 3V 0.2 0.7 mA Idle 8 MHz, VCC = 5V 1.1 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.1.7 ATmega1284 DC Characteristics Table 27-8. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode(3) Power-down mode(3) Notes: Max. Units Active 1 MHz, VCC = 2V 0.38 0.55 mA Active 4 MHz, VCC = 3V 1.8 3.5 mA Active 8 MHz, VCC = 5V 5.6 12 mA Idle 1 MHz, VCC = 2V 0.06 0.5 mA Idle 4 MHz, VCC = 3V 0.2 1.5 mA Idle 8 MHz, VCC = 5V 1.1 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.2 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 27-1, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7 and between 2.7V < VCC < 4.5. Figure 27-1. Maximum Frequency vs. VCC, ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 20 MHz 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.3 Clock Characteristics Table 27-10. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±10% User Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1) -40°C - 85°C ±1% Notes: 1. Voltage range for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. 27.3.1 External Clock Drive Waveforms Figure 27-2. External Clock Drive Waveforms V IH1 V IL1 27.3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.4 System and Reset Characteristics Table 27-12. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter VPOT Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.6 V Power-on Reset Threshold Voltage (falling)(1) 0.6 1.3 1.6 V 0.9VCC V 2.5 µs VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin Condition 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.6 SPI Timing Characteristics See Figure 27-3 on page 336 and Figure 27-4 on page 337 for details. Table 27-15. SPI Timing Parameters Description Mode 1 SCK period Master See Table 17-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 27-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 27.7 MSB 17 ... LSB X 2-wire Serial Interface Characteristics T a b l e 2 7 - 1 6 d e s c r i b e s t h e r e q u i r e m e n t s fo r d ev i c e s c o n n e c t e d t o t h e 2 - w i r e S e r i a l B u s .
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 27-16. 2-wire Serial Bus Requirements (Continued) Symbol Parameter Condition tLOW Low Period of the SCL Clock tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Min Max Units (6) 4.7 – µs (7) 1.3 – µs fSCL ≤ 100 kHz 4.0 – µs fSCL > 100 kHz 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.8 ADC Characteristics Table 27-17. ADC Characteristics, Single Ended Channel Symbol Typ(1) Max(1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 1.9 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3.25 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 27-18.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 27-18. ADC Characteristics, Differential Channels (Continued) Symbol Parameter Gain Error Offset Error Min(1) Gain = 1x VCC =5 V, VREF = 4V ADC clock = 200 kHz 18 Gain = 10x VCC =5 V, VREF = 4V ADC clock = 200 kHz 19 Gain = 200x VCC =5 V, VREF = 4V ADC clock = 200 kHz 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1 28.1.1 ATmega164A Typical Characteristics Active Supply Current Figure 28-1. ATmega164A: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 1.2 5.5 V 1 5.0 V ICC (mA) 0.8 4.5 V 4.0 V 0.6 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-2. ATmega164A: Active Supply Current vs. Frequency (1 - 20 MHz). 12 5.5 V 10 5.0 V 4.5 V ICC (mA) 8 4.0 V 6 4 3.3 V 2.7 V 2 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-3. ATmega164A: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 6 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-4. ATmega164A: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-5. ATmega164A: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.25 -40 °C 25 °C 85 °C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.1.2 Idle Supply Current Figure 28-6. ATmega164A: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 0.2 5.5 V 5.0 V 4.5 V 0.15 ICC (mA) 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-7. ATmega164A: Idle Supply Current vs. VCC (1 - 20 MHz). 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-8. ATmega164A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-9. ATmega164A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.35 -40 °C 25 °C 85 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-10. ATmega164A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 0.1 25 °C 85 °C ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.4 Power-down Supply Current Figure 28-11. ATmega164A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled). 1.6 85 °C 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 25 °C -40 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-12. ATmega164A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled). 10 -40 °C 25 °C 85 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.5 Power-save Supply Current Figure 28-13. ATmega164A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 1.8 1.5 25 °C ICC (uA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.1.6 Standby Supply Current Figure 28-14. ATmega164A: Standby Supply Current vs. VCC (Watchdog Timer Disabled). 0.2 6MHz_xtal 6MHz_res 0.18 0.16 ICC (mA) 0.14 4MHz_res 4MHz_xtal 0.12 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.7 Pin Pull-up Figure 28-15. ATmega164A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V). 50 45 40 IOP (uA) 35 30 25 20 15 25 °C 85 °C -40 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 28-16. ATmega164A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-17. ATmega164A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 40 25 °C 20 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 28-18. ATmega164A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). 35 30 IRESET (uA) 25 20 15 10 25 °C -40 °C 85 °C 5 0 0 0.5 1 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-19. ATmega164A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-20. ATmega164A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.8 Pin Driver Strength Figure 28-21. ATmega164A: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 1 85 °C 0.8 VOL (V) 25 °C 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 28-22. ATmega164A: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-23. ATmega164A: I/O Pin Output Voltage vs. Source Current (VCC = 3V). 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 28-24. ATmega164A: I/O Pin Output Voltage vs. Source Current (VCC = 5V). 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.9 Pin Threshold and Hysteresis Figure 28-25. ATmega164A: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-26. ATmega164A: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-27. ATmega164A: I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-28. ATmega164A: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-29. ATmega164A: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-30. ATmega164A: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.10 BOD Threshold Figure 28-31. ATmega164A: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold (V) 4.3 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-32. ATmega164A: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.78 Rising Vcc Threshold (V) 2.76 2.74 2.72 2.7 Falling Vcc 2.68 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-33. ATmega164A: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.85 Rising Vcc 1.845 1.84 Threshold (V) 1.835 1.83 1.825 1.82 1.815 Falling Vcc 1.81 1.805 1.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-34. ATmega164A: Calibrated Bandgap Voltage vs. VCC 1.109 1.107 Bandgap Voltage (V) 1.105 1.103 25 °C 85 °C 1.101 1.099 1.097 1.095 1.093 -40 °C 1.091 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-35. ATmega164A: Bandgap Voltage vs. Temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap Voltage (V) 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.1.11 Internal Oscillator Speed Figure 28-36. ATmega164A: Watchdog Oscillator Frequency vs. Temperature 134 132 FRC (kHz) 130 128 126 2.1 V 2.7 V 3.3 V 4.0 V 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-37. ATmega164A: Watchdog Oscillator Frequency vs. VCC 135 132 FRC (kHz) -40 °C 129 25 °C 126 123 85 °C 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-38. ATmega164A: Calibrated 8 MHz RC Oscillator vs. VCC 8.4 85 °C 8.2 FRC (MHz) 8 25 °C 7.8 -40 °C 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-39. ATmega164A: Calibrated 8 MHz RC Oscillator vs. Temperature 8.3 5.0 V 3.0 V 8.2 FRC (MHz) 8.1 8 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-40. ATmega164A: Calibrated 8 MHz RC Oscillator vs.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.12 Current Consumption of Peripheral Units Figure 28-41. ATmega164A: ADC Current vs. VCC (AREF = AVCC) 320 -40 °C 85 °C 25 °C 280 240 ICC (uA) 200 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-42. ATmega164A: Analog Comparator Current vs. VCC 100 90 -40 °C 80 25 °C 85 °C ICC (uA) 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-43. ATmega164A: AREF External Reference Current vs. VCC 200 25 °C 85 °C -40 °C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-44. ATmega164A: Brownout Detector Current vs. VCC 27 85 °C 25 °C -40 °C 24 21 ICC (uA) 18 15 12 9 6 3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-45. ATmega164A: Programming Current vs. VCC 12 -40 °C 25 °C 85 °C 10 ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-46. ATmega164A: Watchdog Timer Current vs. VCC 9 -40 °C 8 25 °C 85 °C 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.1.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-47. ATmega164A: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 0.1 5.5 V 0.08 5.0 V ICC (mA) 4.5 V 0.06 4.0 V 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.2 0.4 0.6 0.8 1 Frequency (MHz) Figure 28-48. ATmega164A: Reset Supply Current vs. Frequency (1 - 20 MHz). 1.8 5.5 V 1.5 5.0 V 4.5 V ICC (mA) 1.2 0.9 4.0 V 0.6 3.3 V 0.3 2.7 V 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-49. ATmega164A: Minimum Reset Pulsewidth vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2 28.2.1 ATmega164PA Typical Characteristics Active Supply Current Figure 28-50. ATmega164PA: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 1.2 5.5 V 1 5.0 V ICC (mA) 0.8 4.5 V 4.0 V 0.6 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-51. ATmega164PA: Active Supply Current vs. Frequency (1 - 20 MHz). 12 5.5 V 10 5.0 V 4.5 V ICC (mA) 8 4.0 V 6 4 3.3 V 2.7 V 2 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-52. ATmega164PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 6 85 °C 25 °C -40 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-53. ATmega164PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-54. ATmega164PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.25 -40 °C 25 °C 85 °C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.2.2 Idle Supply Current Figure 28-55. ATmega164PA: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 0.2 5.5 V 5.0 V 4.5 V 0.15 ICC (mA) 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-56. ATmega164PA: Idle Supply Current vs. VCC (1 - 20 MHz). 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-57. ATmega164PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-58. ATmega164PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.35 -40 °C 25 °C 85 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-59. ATmega164PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 0.1 25 °C 85 °C ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.4 Power-down Supply Current Figure 28-60. ATmega164PA: Power-down Supply Current vs. VCC (Watchdog Timer Disabled). 1.6 85 °C 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 25 °C -40 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-61. ATmega164PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled). 10 -40 °C 25 °C 85 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.5 Power-save Supply Current Figure 28-62. ATmega164PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 1.8 1.5 25 °C ICC (uA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.2.6 Standby Supply Current Figure 28-63. ATmega164PA: Standby Supply Current vs. VCC (Watchdog Timer Disabled). 0.2 6MHz_xtal 6MHz_res 0.18 0.16 ICC (mA) 0.14 4MHz_res 4MHz_xtal 0.12 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.7 Pin Pull-up Figure 28-64. ATmega164PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V). 50 45 40 IOP (uA) 35 30 25 20 15 25 °C 85 °C -40 °C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 28-65. ATmega164PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-66. ATmega164PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 40 25 °C 20 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 28-67. ATmega164PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). 35 30 IRESET (uA) 25 20 15 10 25 °C -40 °C 85 °C 5 0 0 0.5 1 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-68. ATmega164PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-69. ATmega164PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.8 Pin Driver Strength Figure 28-70. ATmega164PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 1 85 °C 0.8 VOL (V) 25 °C 0.6 -40 °C 0.4 0.2 0 0 4 8 12 16 20 IOL (mA) Figure 28-71. ATmega164PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-72. ATmega164PA: I/O Pin Output Voltage vs. Source Current (VCC = 3V). 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 4 8 12 16 20 IOH (mA) Figure 28-73. ATmega164PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V). 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.9 Pin Threshold and Hysteresis Figure 28-74. ATmega164PA: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-75. ATmega164PA: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-76. ATmega164PA: I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-77. ATmega164PA: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-78. ATmega164PA: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-79. ATmega164PA: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.10 BOD Threshold Figure 28-80. ATmega164PA: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.34 Rising Vcc 4.32 Threshold (V) 4.3 4.28 4.26 Falling Vcc 4.24 4.22 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-81. ATmega164PA: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.78 Rising Vcc Threshold (V) 2.76 2.74 2.72 2.7 Falling Vcc 2.68 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-82. ATmega164PA: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.85 Rising Vcc 1.845 1.84 Threshold (V) 1.835 1.83 1.825 1.82 1.815 Falling Vcc 1.81 1.805 1.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-83. ATmega164PA: Calibrated Bandgap Voltage vs. VCC 1.109 1.107 Bandgap Voltage (V) 1.105 1.103 25 °C 85 °C 1.101 1.099 1.097 1.095 1.093 -40 °C 1.091 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-84. ATmega164PA: Bandgap Voltage vs. Temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap Voltage (V) 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.2.11 Internal Oscillator Speed Figure 28-85. ATmega164PA: Watchdog Oscillator Frequency vs. Temperature 134 132 FRC (kHz) 130 128 126 2.1 V 2.7 V 3.3 V 4.0 V 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-86. ATmega164PA: Watchdog Oscillator Frequency vs. VCC 135 132 FRC (kHz) -40 °C 129 25 °C 126 123 85 °C 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-87. ATmega164PA: Calibrated 8 MHz RC Oscillator vs. VCC 8.4 85 °C 8.2 FRC (MHz) 8 25 °C 7.8 -40 °C 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-88. ATmega164PA: Calibrated 8 MHz RC Oscillator vs. Temperature 8.3 5.0 V 3.0 V 8.2 FRC (MHz) 8.1 8 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-89. ATmega164PA: Calibrated 8 MHz RC Oscillator vs.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.12 Current Consumption of Peripheral Units Figure 28-90. ATmega164PA: ADC Current vs. VCC (AREF = AVCC) 320 -40 °C 85 °C 25 °C 280 240 ICC (uA) 200 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-91. ATmega164PA: Analog Comparator Current vs. VCC 100 90 -40 °C 80 25 °C 85 °C ICC (uA) 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-92. ATmega164PA: AREF External Reference Current vs. VCC 200 25 °C 85 °C -40 °C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-93. ATmega164PA: Brownout Detector Current vs. VCC 27 85 °C 25 °C -40 °C 24 21 ICC (uA) 18 15 12 9 6 3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-94. ATmega164PA: Programming Current vs. VCC 12 -40 °C 25 °C 85 °C 10 ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-95. ATmega164PA: Watchdog Timer Current vs. VCC 9 -40 °C 8 25 °C 85 °C 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.2.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-96. ATmega164PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 0.1 5.5 V 0.08 5.0 V ICC (mA) 4.5 V 0.06 4.0 V 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.2 0.4 0.6 0.8 1 Frequency (MHz) Figure 28-97. ATmega164PA: Reset Supply Current vs. Frequency (1 - 20 MHz). 1.8 5.5 V 1.5 5.0 V 4.5 V ICC (mA) 1.2 0.9 4.0 V 0.6 3.3 V 0.3 2.7 V 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-98. ATmega164PA: Minimum Reset Pulsewidth vs. VCC 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3 28.3.1 ATmega324A Typical Characteristics Active Supply Current Figure 28-99. ATmega324A: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). ICC (mA) 1.2 5.5 V 1 5.0 V 0.8 4.5 V 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-100.ATmega324A: Active Supply Current vs. Frequency (1 - 20 MHz). ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-101.ATmega324A: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 7 85 °C 25 °C -40 °C 6 ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-102.ATmega324A: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.6 85 °C 25 °C -40 °C ICC (mA) 1.2 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-103.ATmega324A: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.25 -40 °C 25 °C 85 °C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.3.2 Idle Supply Current Figure 28-104.ATmega324A: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 5.5 V 0.25 5.0 V 0.2 4.5 V ICC (mA) 4.0 V 0.15 3.3 V 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-105.ATmega324A: Idle Supply Current vs. VCC (1 - 20 MHz). 4 5.5 V 5.0 V 3 ICC (mA) 4.5 V 2 4.0 V 3.3 V 1 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-106.ATmega324A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.8 85 °C 25 °C -40 °C 1.5 ICC (mA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-107.ATmega324A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 85 °C 25 °C -40 °C 0.6 0.5 ICC (mA) 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-108.ATmega324A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.4 Power-down Supply Current Figure 28-109.ATmega324A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled). 1.2 85 °C 1 ICC (uA) 0.8 0.6 0.4 25 °C -40 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-110.ATmega324A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled). 10 -40 °C 85 °C 25 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.5 Power-save Supply Current Figure 28-111.ATmega324A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled andWATCHDOG 32 kHz Crystal Oscillatorand Running). TIMER DISABLED 32 kHz CRYSTAL OSCILLATOR RUNNING 2.50 85 °C 2.00 ICC (uA) 1.50 25 °C -40 °C 1.00 0.50 0.00 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.3.6 Standby Supply Current Figure 28-112.ATmega324A: Standby Supply Current vs. VCC (Watchdog Timer Disabled). 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.7 Pin Pull-up Figure 28-113.ATmega324A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V). 50 IOP (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 28-114.ATmega324A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 25 °C 20 85 °C 10 -40 °C 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-115.ATmega324A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 25 °C 40 85 °C 20 -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 28-116.ATmega324A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). 35 30 IRESET (uA) 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-117.ATmega324A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-118.ATmega324A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.8 Pin Driver Strength Figure 28-119.ATmega324A: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 5 8 11 14 17 20 IOL(mA) Figure 28-120.ATmega324A: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-121.ATmega324A: I/O Pin Output Voltage vs. Source Current (VCC = 3V). 3 2.5 -40 °C 25 °C 85 °C VOH (V) 2 1.5 1 0.5 0 5 8 11 14 17 20 IOH(mA) Figure 28-122.ATmega324A: I/O Pin Output Voltage vs. Source Current (VCC = 5V). 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.9 Pin Threshold and Hysteresis Figure 28-123.ATmega324A: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 85 °C 3 -40 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-124.ATmega324A: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-125.ATmega324A: I/O Pin Input Hysteresis vs. VCC 0.6 85 °C 25 °C 0.5 Input Hysteresis (mV) -40 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-126.ATmega324A: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). , -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-127.ATmega324A: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). -40 °C 25 °C 2.5 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-128.ATmega324A: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.10 BOD Threshold Figure 28-129.ATmega324A: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.4 Rising Vcc 4.38 Threshold (V) 4.36 4.34 4.32 Falling Vcc 4.3 4.28 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-130.ATmega324A: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.8 Rising Vcc 2.78 Threshold (V) 2.76 2.74 Falling Vcc 2.72 2.7 2.68 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-131.ATmega324A: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold (V) 1.84 1.82 Falling Vcc 1.8 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-132.ATmega324A: Calibrated Bandgap Voltage vs. VCC 1.098 1.096 Bandgap Voltage (V) 1.094 1.092 85 °C 25 °C 1.09 1.088 1.086 1.084 1.082 1.08 -40 °C 1.078 1.076 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-133.ATmega324A: Bandgap Voltage vs. Temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap Voltage (V) 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.3.11 Internal Oscillator Speed Figure 28-134.ATmega324A: Watchdog Oscillator Frequency vs. Temperature 122 FRC (kHz) 119 116 2.1 V 2.7 V 3.3 V 4.0 V 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-135.ATmega324A: Watchdog Oscillator Frequency vs. VCC 123 -40 °C FRC (kHz) 120 25 °C 117 114 85 °C 111 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-136.ATmega324A: Calibrated 8 MHz RC Oscillator vs. VCC 8.6 85 °C 8.2 FRC (MHz) 25 °C 7.8 -40 °C 7.4 7 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-137.ATmega324A: Calibrated 8 MHz RC Oscillator vs. Temperature 8.6 5.0 V 3.0 V FRC (MHz) 8.3 8 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-138.ATmega324A: Calibrated 8 MHz RC Oscillator vs.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.12 Current Consumption of Peripheral Units Figure 28-139.ATmega324A: ADC Current vs. VCC (AREF = AVCC) 300 25 °C 85 °C -40 °C 250 ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-140.ATmega324A: Analog Comparator Current vs. VCC 90 -40 °C 80 25 °C 70 85 °C ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-141.ATmega324A: AREF External Reference Current vs. VCC 25 °C 85 °C -40 °C 200 ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-142.ATmega324A: Brownout Detector Current vs. VCC 25 85 °C 25 °C -40 °C ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-143.ATmega324A: Programming Current vs. VCC 14 25 °C -40 °C 85 °C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-144.ATmega324A: Watchdog Timer Current vs. VCC 9 -40 °C 25 °C 85 °C ICC (uA) 7 5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.3.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-145.ATmega324A: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.14 5.5 V 0.12 5.0 V 0.1 ICC (mA) 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-146.ATmega324A: Reset Supply Current vs. Frequency (1 - 20 MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-147.ATmega324A: Minimum Reset Pulsewidth vs. VCC 1800 Pulsewidth (ns) 1500 1200 900 600 85 °C 25 °C -40 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4 28.4.1 ATmega324PA Typical Characteristics Active Supply Current Figure 28-148.ATmega324PA: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). ICC (mA) 1.2 5.5 V 1 5.0 V 0.8 4.5 V 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-149.ATmega324PA: Active Supply Current vs. Frequency (1 - 20 MHz). ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-150.ATmega324PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 7 85 °C 25 °C -40 °C 6 ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-151.ATmega324PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.6 85 °C 25 °C -40 °C ICC (mA) 1.2 0.8 0.4 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-152.ATmega324PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.25 -40 °C 25 °C 85 °C ICC (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.4.2 Idle Supply Current Figure 28-153.ATmega324PA: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 5.5 V 0.25 5.0 V 0.2 4.5 V ICC (mA) 4.0 V 0.15 3.3 V 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-154.ATmega324PA: Idle Supply Current vs. VCC (1 - 20 MHz). 4 5.5 V 5.0 V 3 ICC (mA) 4.5 V 2 4.0 V 3.3 V 1 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-155.ATmega324PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.8 85 °C 25 °C -40 °C 1.5 ICC (mA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-156.ATmega324PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 85 °C 25 °C -40 °C 0.6 0.5 ICC (mA) 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-157.ATmega324PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.4 Power-down Supply Current Figure 28-158.ATmega324PA: Power-down Supply Current vs. VCC (Watchdog Timer Disabled). 1.2 85 °C 1 ICC (uA) 0.8 0.6 0.4 25 °C -40 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-159.ATmega324PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled). 10 -40 °C 85 °C 25 °C ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.5 Power-save Supply Current Figure 28-160.ATmega324PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled andWATCHDOG 32 kHz Crystal Oscillatorand Running). TIMER DISABLED 32 kHz CRYSTAL OSCILLATOR RUNNING 2.50 85 °C 2.00 ICC (uA) 1.50 25 °C -40 °C 1.00 0.50 0.00 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.4.6 Standby Supply Current Figure 28-161.ATmega324PA: Standby Supply Current vs. VCC (Watchdog Timer Disabled). 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.7 Pin Pull-up Figure 28-162.ATmega324PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V). 50 IOP (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 28-163.ATmega324PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 25 °C 20 85 °C 10 -40 °C 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-164.ATmega324PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 25 °C 40 85 °C 20 -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 28-165.ATmega324PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). 35 30 IRESET (uA) 25 20 15 10 25 °C 5 -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-166.ATmega324PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-167.ATmega324PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V).
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.8 Pin Driver Strength Figure 28-168.ATmega324PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 1 85 °C 0.8 25 °C VOL (V) 0.6 -40 °C 0.4 0.2 0 5 8 11 14 17 20 IOL(mA) Figure 28-169.ATmega324PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-170.ATmega324PA: I/O Pin Output Voltage vs. Source Current (VCC = 3V). 3 2.5 -40 °C 25 °C 85 °C VOH (V) 2 1.5 1 0.5 0 5 8 11 14 17 20 IOH(mA) Figure 28-171.ATmega324PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V). 4.9 4.8 VOH (V) 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.9 Pin Threshold and Hysteresis Figure 28-172.ATmega324PA: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 85 °C 3 -40 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-173.ATmega324PA: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-174.ATmega324PA: I/O Pin Input Hysteresis vs. VCC 0.6 85 °C 25 °C 0.5 Input Hysteresis (mV) -40 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-175.ATmega324PA: Reset Pin, Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-176.ATmega324PA: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). -40 °C 25 °C 2.5 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-177.ATmega324PA: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.10 BOD Threshold Figure 28-178.ATmega324PA: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.4 Rising Vcc 4.38 Threshold (V) 4.36 4.34 4.32 Falling Vcc 4.3 4.28 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-179.ATmega324PA: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.8 Rising Vcc 2.78 Threshold (V) 2.76 2.74 Falling Vcc 2.72 2.7 2.68 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-180.ATmega324PA: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.86 Rising Vcc Threshold (V) 1.84 1.82 Falling Vcc 1.8 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-181.ATmega324PA: Calibrated Bandgap Voltage vs. VCC 1.098 1.096 Bandgap Voltage (V) 1.094 1.092 85 °C 25 °C 1.09 1.088 1.086 1.084 1.082 1.08 -40 °C 1.078 1.076 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-182.ATmega324PA: Bandgap Voltage vs. Temperature 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap Voltage (V) 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.4.11 Internal Oscillator Speed Figure 28-183.ATmega324PA: Watchdog Oscillator Frequency vs. Temperature 122 FRC (kHz) 119 116 2.1 V 2.7 V 3.3 V 4.0 V 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-184.ATmega324PA: Watchdog Oscillator Frequency vs. VCC 123 -40 °C FRC (kHz) 120 25 °C 117 114 85 °C 111 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-185.ATmega324PA: Calibrated 8 MHz RC Oscillator vs. VCC 8.6 85 °C 8.2 FRC (MHz) 25 °C 7.8 -40 °C 7.4 7 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-186.ATmega324PA: Calibrated 8 MHz RC Oscillator vs. Temperature 8.6 5.0 V 3.0 V FRC (MHz) 8.3 8 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 28-187.ATmega324PA: Calibrated 8 MHz RC Oscillator vs.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.12 Current Consumption of Peripheral Units Figure 28-188.ATmega324PA: ADC Current vs. VCC (AREF = AVCC) 300 25 °C 85 °C -40 °C 250 ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-189.ATmega324PA: Analog Comparator Current vs. VCC 90 -40 °C 80 25 °C 70 85 °C ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-190.ATmega324PA: AREF External Reference Current vs. VCC 25 °C 85 °C -40 °C 200 ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-191.ATmega324PA: Brownout Detector Current vs. VCC 25 85 °C 25 °C -40 °C ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-192.ATmega324PA: Programming Current vs. VCC 14 25 °C -40 °C 85 °C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-193.ATmega324PA: Watchdog Timer Current vs. VCC 9 -40 °C 25 °C 85 °C ICC (uA) 7 5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.4.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-194.ATmega324PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.14 5.5 V 0.12 5.0 V 0.1 ICC (mA) 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-195.ATmega324PA: Reset Supply Current vs. Frequency (1 - 20 MHz) 2.5 5.5 V 2 5.0 V ICC (mA) 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-196.ATmega324PA: Minimum Reset Pulsewidth vs. VCC 1800 Pulsewidth (ns) 1500 1200 900 600 85 °C 25 °C -40 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5 28.5.1 ATmega644A Typical Characteristics Active Supply Current Figure 28-197.ATmega644A: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 1.2 5.5 V 1 5.0 V 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-198.ATmega644A: Active Supply Current vs. Frequency (1 - 20 MHz). ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-199.ATmega644A: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 7 85°C 25°C -40°C 6 ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-200.ATmega644A: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-201.ATmega644A: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.22 -40 °C 25 °C 85 °C 0.2 0.18 ICC (mA) 0.16 0.14 0.12 0.1 0.08 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.5.2 Idle Supply Current Figure 28-202.ATmega644A: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 0.24 5.5 V 0.2 5.0 V 4.5 V 4.0 V ICC (mA) 0.16 3.3 V 2.7 V 0.12 0.08 1.8 V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-203.ATmega644A: Idle Supply Current vs. VCC (1 - 20 MHz). 3 5.5 V 5.0 V 2.5 4.5 V ICC (mA) 2 4.0 V 1.5 1 3.3 V 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-204.ATmega644A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-205.ATmega644A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-206.ATmega644A: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-9.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.4 Power-down Supply Current Figure 28-207.ATmega644A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.5 85 °C ICC (uA) 2 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-208.ATmega644A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 9 85 °C 8 -40 °C 25 °C ICC (uA) 7 6 5 4 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.5 Power-save Supply Current Figure 28-209.ATmega644A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running) 2.5 85 °C 2 Icc(uA) 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.5.6 Standby Supply Current Figure 28-210.ATmega644A: Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC (mA) 0.1 0.08 2MHz_res 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.7 Pin Pull-up Figure 28-211.ATmega644A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 25 °C 85 °C -40 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 28-212.ATmega644A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-213.ATmega644A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 28-214.ATmega644A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). g p g ( ) 35 30 IRESET (uA) 25 20 15 10 25 °C -40 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
PAGE 457
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-215.ATmega644A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-216.ATmega644A: Reset Pull-up Resistor Current vs.
PAGE 458
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.8 Pin Driver Strength Figure 28-217.ATmega644A: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 0.9 85 °C 0.8 0.7 25 °C 0.6 VOL (V) -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 28-218.ATmega644A: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
PAGE 459
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-219.ATmega644A: I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 28-220.ATmega644A: I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
PAGE 460
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.9 Pin Threshold and Hysteresis Figure 28-221.ATmega644A: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 85 °C -40 °C 25 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-222.ATmega644A: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 461
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-223.ATmega644A: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (mV) 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-224.ATmega644A: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 462
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-225.ATmega644A: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-226.ATmega644A: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 463
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.10 BOD Threshold Figure 28-227.ATmega644A: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold (V) 4.32 4.29 Falling Vcc 4.26 4.23 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-228.ATmega644A: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold (V) 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 464
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-229.ATmega644A: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold (V) 1.82 1.81 1.8 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 28-230.ATmega644A: Calibrated Bandgap Voltage vs. VCC 1.086 1.084 Bandgap Voltage (V) 1.082 85 °C 25 °C 1.08 1.078 1.076 1.074 1.072 1.07 1.068 -40 °C 1.066 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 465
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-231.ATmega644A: Bandgap Voltage vs. Temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap Voltage (V) 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.5.11 Internal Oscillator Speed Figure 28-232.ATmega644A: Watchdog Oscillator Frequency vs. Temperature 119 118 117 116 FRC (kHz) 115 114 113 2.1 V 112 2.7 V 3.3 V 4.0 V 5.
PAGE 466
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-233.ATmega644A: Watchdog Oscillator Frequency vs. VCC 119 118 117 -40 °C 116 FRC (kHz) 115 25 °C 114 113 112 111 110 85 °C 109 108 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-234.ATmega644A: Calibrated 8 MHz RC Oscillator vs. VCC 8.4 85 °C 8.2 25 °C FRC (MHz) 8 -40 °C 7.8 7.6 7.4 7.2 2 2.5 3 3.5 4 4.5 5 5.
PAGE 467
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-235.ATmega644A: Calibrated 8 MHz RC Oscillator vs. Temperature 8.4 5.0 V 8.3 3.0 V FRC (MHz) 8.2 8.1 8 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Figure 28-236.ATmega644A: Calibrated 8 MHz RC Oscillator vs.
PAGE 468
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.12 Current Consumption of Peripheral Units Figure 28-237.ATmega644A: ADC Current vs. VCC (AREF = AVCC) 250 25 °C 85 °C -40 °C ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) Figure 28-238.ATmega644A: Analog Comparator Current vs. VCC 90 -40°C 80 25°C 85°C ICC (uA) 70 60 50 40 30 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 469
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-239.ATmega644A: AREF External Reference Current vs. VCC 200 25 °C 85 °C -40 °C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-240.ATmega644A: Brownout Detector Current vs. VCC 24 85 °C 22 25 °C -40 °C ICC (uA) 20 18 16 14 12 2 2.5 3 3.5 4 4.5 5 5.
PAGE 470
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-241.ATmega644A: Programming Current vs. VCC -40 °C 16 14 12 ICC (mA) 10 25 °C 8 85 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-242.ATmega644A: Watchdog Timer Current vs. VCC 9 8 -40 °C 7 25 °C 85 °C ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 471
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.5.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-243.ATmega644A: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.1 5.5 V 5.0 V 0.08 ICC (mA) 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-244.ATmega644A: Reset Supply Current vs. Frequency (1 - 20 MHz) 2 5.5 V 1.75 5.0 V 1.5 4.5 V ICC (mA) 1.25 1 4.0 V 0.75 3.3 V 0.5 2.7 V 0.25 1.
PAGE 472
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-245.ATmega644A: Minimum Reset Pulsewidth vs. VCC 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 85 °C 25 °C -40 °C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 473
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6 28.6.1 ATmega644PA Typical Characteristics Active Supply Current Figure 28-246.ATmega644PA: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 1.2 5.5 V 1 5.0 V 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-247.ATmega644PA: Active Supply Current vs. Frequency (1 - 20 MHz). ICC (mA) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
PAGE 474
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-248.ATmega644PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 7 85°C 25°C -40°C 6 ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-249.ATmega644PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 475
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-250.ATmega644PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.22 -40 °C 25 °C 85 °C 0.2 0.18 ICC (mA) 0.16 0.14 0.12 0.1 0.08 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.6.2 Idle Supply Current Figure 28-251.ATmega644PA: Idle Supply Current vs. VCC (0.1 - 1.0 MHz). 0.24 5.5 V 0.2 5.0 V 4.5 V 4.0 V ICC (mA) 0.16 3.3 V 2.7 V 0.12 0.08 1.8 V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 476
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-252.ATmega644PA: Idle Supply Current vs. VCC (1 - 20 MHz). 3 5.5 V 5.0 V 2.5 4.5 V ICC (mA) 2 4.0 V 1.5 1 3.3 V 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-253.ATmega644PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 1.4 85 °C 25 °C -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 477
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-254.ATmega644PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.35 85 °C 25 °C -40 °C 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-255.ATmega644PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 478
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-11.
PAGE 479
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.4 Power-down Supply Current Figure 28-256.ATmega644PA: Power-down Supply Current vs. VCC (Watchdog Timer Disabled). 2.5 85 °C ICC (uA) 2 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-257.ATmega644PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled). 9 85 °C 8 -40 °C 25 °C ICC (uA) 7 6 5 4 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 480
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.5 Power-save Supply Current Figure 28-258.ATmega644PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 2.5 85 °C 2 Icc(uA) 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.6.6 Standby Supply Current Figure 28-259.ATmega644PA: Standby Supply Current vs. VCC (Watchdog Timer Disabled). 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC (mA) 0.1 0.08 2MHz_res 0.
PAGE 481
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.7 Pin Pull-up Figure 28-260.ATmega644PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V). 50 45 40 IOP (uA) 35 30 25 20 15 10 25 °C 85 °C -40 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 28-261.ATmega644PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V). 80 70 60 IOP (uA) 50 40 30 20 25 °C 85 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
PAGE 482
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-262.ATmega644PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V). 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -40 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 28-263.ATmega644PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V). g p g ( ) 35 30 IRESET (uA) 25 20 15 10 25 °C -40 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
PAGE 483
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-264.ATmega644PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V). 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-265.ATmega644PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V).
PAGE 484
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.8 Pin Driver Strength Figure 28-266.ATmega644PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V). 0.9 85 °C 0.8 0.7 25 °C 0.6 VOL (V) -40 °C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 28-267.ATmega644PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V). 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.
PAGE 485
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-268.ATmega644PA: I/O Pin Output Voltage vs. Source Current (VCC = 3V). 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 28-269.ATmega644PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V). 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.
PAGE 486
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.9 Pin Threshold and Hysteresis Figure 28-270.ATmega644PA: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 3 85 °C -40 °C 25 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-271.ATmega644PA: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 487
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-272.ATmega644PA: I/O Pin Input Hysteresis vs. VCC 0.6 25 °C 85 °C -40 °C Input Hysteresis (mV) 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-273.ATmega644PA: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’). 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 488
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-274.ATmega644PA: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-275.ATmega644PA: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 489
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.10 BOD Threshold Figure 28-276.ATmega644PA: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.35 Rising Vcc Threshold (V) 4.32 4.29 Falling Vcc 4.26 4.23 4.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-277.ATmega644PA: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.77 Rising Vcc 2.75 Threshold (V) 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 490
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-278.ATmega644PA: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.84 1.83 Rising Vcc Threshold (V) 1.82 1.81 1.8 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 28-279.ATmega644PA: Calibrated Bandgap Voltage vs. VCC 1.086 1.084 Bandgap Voltage (V) 1.082 85 °C 25 °C 1.08 1.078 1.076 1.074 1.072 1.07 1.068 -40 °C 1.066 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 491
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-280.ATmega324PA: Bandgap Voltage vs. Temperature 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap Voltage (V) 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 28.6.11 Internal Oscillator Speed Figure 28-281.ATmega644PA: Watchdog Oscillator Frequency vs. Temperature 119 118 117 116 FRC (kHz) 115 114 113 2.1 V 112 2.7 V 3.3 V 4.0 V 5.
PAGE 492
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-282.ATmega644PA: Watchdog Oscillator Frequency vs. VCC 119 118 117 -40 °C 116 FRC (kHz) 115 25 °C 114 113 112 111 110 85 °C 109 108 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-283.ATmega644PA: Calibrated 8 MHz RC Oscillator vs. VCC 8.4 85 °C 8.2 25 °C FRC (MHz) 8 -40 °C 7.8 7.6 7.4 7.2 2 2.5 3 3.5 4 4.5 5 5.
PAGE 493
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-284.ATmega644PA: Calibrated 8 MHz RC Oscillator vs. Temperature 8.4 5.0 V 8.3 3.0 V FRC (MHz) 8.2 8.1 8 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Figure 28-285.ATmega644PA: Calibrated 8 MHz RC Oscillator vs.
PAGE 494
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.12 Current Consumption of Peripheral Units Figure 28-286.ATmega644PA: ADC Current vs. VCC (AREF = AVCC) 250 25 °C 85 °C -40 °C ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) Figure 28-287.ATmega644PA: Analog Comparator Current vs. VCC 90 -40°C 80 25°C 85°C ICC (uA) 70 60 50 40 30 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 495
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-288.ATmega644PA: AREF External Reference Current vs. VCC 200 25 °C 85 °C -40 °C ICC (uA) 160 120 80 40 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-289.ATmega644PA: Brownout Detector Current vs. VCC 24 85 °C 22 25 °C -40 °C ICC (uA) 20 18 16 14 12 2 2.5 3 3.5 4 4.5 5 5.
PAGE 496
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-290.ATmega644PA: Programming Current vs. VCC -40 °C 16 14 12 ICC (mA) 10 25 °C 8 85 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-291.ATmega644PA: Watchdog Timer Current vs. VCC 9 8 -40 °C 7 25 °C 85 °C ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 497
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.6.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-292.ATmega644PA: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.1 5.5 V 5.0 V 0.08 ICC (mA) 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-293.ATmega644PA: Reset Supply Current vs. Frequency (1 - 20 MHz) 2 5.5 V 1.75 5.0 V 1.5 4.5 V ICC (mA) 1.25 1 4.0 V 0.75 3.3 V 0.5 2.7 V 0.25 1.
PAGE 498
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-294.ATmega644PA: Minimum Reset Pulsewidth vs. VCC 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 85 °C 25 °C -40 °C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 499
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7 28.7.1 ATmega1284 Typical Characteristics Active Supply Current ICC (mA) Figure 28-295.ATmega1284: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 1.6 5.5 V 1.4 5.0 V 1.2 4.5 V 1 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-296.ATmega1284: Active Supply Current vs. Frequency (1 - 20 MHz) 20 5.5 V 18 5.0 V 16 4.5 V ICC (mA) 14 12 4.0 V 10 8 3.
PAGE 500
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-297.ATmega1284: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 9 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-298.ATmega1284: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.8 85 °C 25 °C -40 °C 1.5 ICC (mA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 501
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-299.ATmega1284: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.28 -40 °C 25 °C 85 °C 0.24 ICC (mA) 0.2 0.16 0.12 0.08 0.04 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.7.2 Idle Supply Current Figure 28-300.ATmega1284: Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.24 5.5 V 0.21 5.0 V 0.18 4.5 V 4.0 V 3.6 V ICC (mA) 0.15 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 502
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-301.ATmega1284: Idle Supply Current vs. Frequency (1 - 20 MHz) 3 5.5 V 2.5 5.0 V 4.5 V ICC (mA) 2 1.5 4.0 V 1 2.7 V 0.5 3.3 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-302.ATmega1284: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.4 85 °C 1.2 25 °C -40 °C ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 503
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-303.ATmega1284: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.42 85 °C 25 °C -40 °C 0.36 ICC (mA) 0.3 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-304.ATmega1284: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.12 -40 °C 85 °C 25 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 504
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-13.
PAGE 505
164A/164PA/324A/324PA/644A/644PA/1284/1284P I CC total ≈ 0.075 mA ⋅ (1+ 0.08 + 0.198 + 0.132) ≈ 0.106 mA 28.7.4 Power-down Supply Current Figure 28-305.ATmega1284: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85 °C 3.5 3 ICC (uA) 2.5 2 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-306.ATmega1284: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 11 85 °C 10.2 9.4 ICC (uA) 8.6 -40 °C 25 °C 7.8 7 6.2 5.4 4.6 3.8 3 1.5 2 2.5 3 3.
PAGE 506
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7.5 Power-save Supply Current Figure 28-307.ATmega1284: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running) 5.0 85 °C 4.5 4.0 ICC (uA) 3.5 3.0 2.5 2.0 1.5 25 °C -40 °C 1.0 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.7.6 Standby Supply Current Figure 28-308.ATmega1284: Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.25 6MHz_xtal ICC (mA) 0.2 6MHz_res 4MHz_xtal 4MHz_res 2MHz_xtal 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7.7 Pin Pull-up Figure 28-309.ATmega1284: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Figure 28-310.ATmega1284: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-311.ATmega1284: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 28-312.ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-313.ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-314.ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
PAGE 510
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7.8 Pin Driver Strength Figure 28-315.ATmega1284: I/O Pin Output Voltage vs. Sink Current (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -40 °C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 28-316.ATmega1284: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 0.9 85 °C 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.
PAGE 511
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-317.ATmega1284: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL(mA) Figure 28-318.ATmega1284: I/O Pin Output Voltage vs. Source Current (VCC = 2.7V) 3 VOH (V) 2.5 2 -40 °C 25 °C 1.5 85 °C 1 0.
PAGE 512
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-319.ATmega1284: I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 28.7.9 Pin Threshold and Hysteresis Figure 28-320.ATmega1284: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 513
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-321.ATmega1284: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 85 °C -40 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-322.ATmega1284: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.55 85 °C 25 °C -40 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 514
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-323.ATmega1284: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-324.ATmega1284: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 -40 °C 85 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 515
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-325.ATmega1284: Reset Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 -40 °C 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.7.10 BOD Threshold Figure 28-326.ATmega1284: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold (V) 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-327.ATmega1284: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.78 Rising Vcc Threshold (V) 2.76 2.74 2.72 2.7 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-328.ATmega1284: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.84 Rising Vcc Threshold (V) 1.83 1.82 1.81 Falling Vcc 1.8 1.79 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-329.ATmega1284: Calibrated Bandgap Voltage vs. VCC 1.12 Bandgap Voltage (V) 1.115 85 °C 25 °C 1.11 1.105 1.1 1.095 -40 °C 1.09 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-330.ATmega1284: Bandgap Voltage vs. Temperature 1.12 1.8V 3.3V 5V 5.5V Bandgap Voltage (V) 1.115 1.11 1.105 1.1 1.095 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.7.11 Internal Oscillator Speed Figure 28-331.ATmega1284: Watchdog Oscillator Frequency vs. Temperature 123 122 121 FRC (kHz) 120 119 118 117 2.7 V 116 3.3 V 4.0 V 5.5 V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-332.ATmega1284: Watchdog Oscillator Frequency vs. VCC 124 122 FRC (kHz) -40 °C 120 25 °C 118 116 85 °C 114 2 2.5 3 3.5 4 4.5 5 5.
PAGE 519
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-333.ATmega1284: Calibrated 8 MHz RC Oscillator vs. VCC 8.6 85 °C 8.4 25 °C FRC (MHz) 8.2 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-334.ATmega1284: Calibrated 8 MHz RC Oscillator vs. Temperature 8.3 5.5 V 8.2 3.3 V 2.7 V FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-335.ATmega1284: Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 16 85 °C 25 °C -40 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 28.7.12 Current Consumption of Peripheral Units Figure 28-336.ATmega1284: ADC Current vs. VCC (AREF = AVCC) 280 -40 °C 25 °C 85 °C 260 240 ICC (uA) 220 200 180 160 140 120 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 521
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-337.ATmega1284: Analog Comparator Current vs. VCC 85 -40 °C 25 °C 85 °C 75 ICC (uA) 65 55 45 35 25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-338.ATmega1284: AREF External Reference Current vs. VCC 200 85 °C 25 °C -40 °C 180 ICC (uA) 160 140 120 100 80 60 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 522
164A/164PA/324A/324PA/644A/644PA/1284/1284P ICC (uA) Figure 28-339.ATmega1284: Brownout Detector Current vs. VCC 25 85 °C 23 25 °C 21 -40 °C 19 17 15 13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-340.ATmega1284: Programming Current vs. VCC 14 -40 °C 12 ICC (mA) 10 25 °C 8 85 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 523
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-341.ATmega1284: Watchdog Timer Current vs. VCC 8.5 -40 °C 7.5 25 °C 85 °C ICC (uA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.7.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-342.ATmega1284: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.1 5.5 V 5.0 V 0.08 ICC (mA) 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 524
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-343.ATmega1284: Reset Supply Current vs. Frequency (1 - 20 MHz) 1.6 5.5 V 1.4 5.0 V 1.2 4.5 V ICC (mA) 1 0.8 4.0 V 0.6 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-344.ATmega1284: Minimum Reset Pulsewidth vs. VCC 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8 28.8.1 ATmega1284P Typical Characteristics Active Supply Current ICC (mA) Figure 28-345.ATmega1284P: Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 1.6 5.5 V 1.4 5.0 V 1.2 4.5 V 1 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-346.ATmega1284P: Active Supply Current vs. Frequency (1 - 20 MHz) 20 5.5 V 18 5.0 V 16 4.5 V ICC (mA) 14 12 4.0 V 10 8 3.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-347.ATmega1284P: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 9 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-348.ATmega1284P: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.8 85 °C 25 °C -40 °C 1.5 ICC (mA) 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 527
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-349.ATmega1284P: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.28 -40 °C 25 °C 85 °C 0.24 ICC (mA) 0.2 0.16 0.12 0.08 0.04 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.8.2 Idle Supply Current Figure 28-350.ATmega1284P: Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.24 5.5 V 0.21 5.0 V 0.18 4.5 V 4.0 V 3.6 V ICC (mA) 0.15 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 528
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-351.ATmega1284P: Idle Supply Current vs. Frequency (1 - 20 MHz) 3 5.5 V 2.5 5.0 V 4.5 V ICC (mA) 2 1.5 4.0 V 1 2.7 V 0.5 3.3 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-352.ATmega1284P: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.4 85 °C 1.2 25 °C -40 °C ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 529
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-353.ATmega1284P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.42 85 °C 25 °C -40 °C 0.36 ICC (mA) 0.3 0.24 0.18 0.12 0.06 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-354.ATmega1284P: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.12 -40 °C 85 °C 25 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 530
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 49 for details. Table 28-15.
PAGE 531
164A/164PA/324A/324PA/644A/644PA/1284/1284P I CC total ≈ 0.075 mA ⋅ (1+ 0.08 + 0.198 + 0.132) ≈ 0.106 mA 28.8.4 Power-down Supply Current Figure 28-355.ATmega1284P: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85 °C 3.5 3 ICC (uA) 2.5 2 1.5 1 0.5 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-356.ATmega1284P: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 11 85 °C 10.2 9.4 ICC (uA) 8.6 -40 °C 25 °C 7.8 7 6.2 5.4 4.6 3.8 3 1.5 2 2.5 3 3.
PAGE 532
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8.5 Power-save Supply Current Figure 28-357.ATmega1284P: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running) 5.0 85 °C 4.5 4.0 ICC (uA) 3.5 3.0 2.5 2.0 1.5 25 °C -40 °C 1.0 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.8.6 Standby Supply Current Figure 28-358.ATmega1284P: Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.25 6MHz_xtal ICC (mA) 0.
PAGE 533
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8.7 Pin Pull-up Figure 28-359.ATmega1284P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Figure 28-360.ATmega1284P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
PAGE 534
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-361.ATmega1284P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (uA) 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 28-362.ATmega1284P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (uA) 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
PAGE 535
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-363.ATmega1284P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 28-364.ATmega1284P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
PAGE 536
164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8.8 Pin Driver Strength Figure 28-365.ATmega1284P: I/O Pin Output Voltage vs. Sink Current (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -40 °C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 28-366.ATmega1284P: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 0.9 85 °C 0.8 0.7 25 °C VOL (V) 0.6 -40 °C 0.5 0.4 0.3 0.2 0.
PAGE 537
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-367.ATmega1284P: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 85 °C 0.5 25 °C VOL (V) 0.4 -40 °C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL(mA) Figure 28-368.ATmega1284P: I/O Pin Output Voltage vs. Source Current (VCC = 2.7V) 3 VOH (V) 2.5 2 -40 °C 25 °C 1.5 85 °C 1 0.
PAGE 538
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-369.ATmega1284P: I/O Pin Output Voltage vs. Source Current (VCC = 3V) 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 28.8.9 Pin Threshold and Hysteresis Figure 28-370.ATmega1284P: I/O Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) 3 85 °C 25 °C -40 °C Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 539
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-371.ATmega1284P: I/O Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 85 °C -40 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-372.ATmega1284P: I/O Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.55 85 °C 25 °C -40 °C 0.5 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 540
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-373.ATmega1284P: Reset Pin Input Threshold vs. VCC (VIH , I/O Pin Read as ‘1’) -40 °C 85 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-374.ATmega1284P: Reset Pin Input Threshold vs. VCC (VIL, I/O Pin Read as ‘0’) 2.5 -40 °C 85 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
PAGE 541
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-375.ATmega1284P: Reset Pin Input Hysteresis vs. VCC 0.6 Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 -40 °C 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.8.10 BOD Threshold Figure 28-376.ATmega1284P: BOD Threshold vs. Temperature (VBOT = 4.3V) 4.37 Rising Vcc 4.35 Threshold (V) 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-377.ATmega1284P: BOD Threshold vs. Temperature (VBOT = 2.7V) 2.78 Rising Vcc Threshold (V) 2.76 2.74 2.72 2.7 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-378.ATmega1284P: BOD Threshold vs. Temperature (VBOT = 1.8V) 1.84 Rising Vcc Threshold (V) 1.83 1.82 1.81 Falling Vcc 1.8 1.79 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-379.ATmega1284P: Calibrated Bandgap Voltage vs. VCC 1.12 Bandgap Voltage (V) 1.115 85 °C 25 °C 1.11 1.105 1.1 1.095 -40 °C 1.09 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-380.ATmega1284P: Bandgap Voltage vs. Temperature 1.12 1.8V 3.3V 5V 5.5V Bandgap Voltage (V) 1.115 1.11 1.105 1.1 1.095 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 28.8.11 Internal Oscillator Speed Figure 28-381.ATmega1284P: Watchdog Oscillator Frequency vs. Temperature 123 122 121 FRC (kHz) 120 119 118 117 2.7 V 116 3.3 V 4.0 V 5.5 V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 28-382.ATmega1284P: Watchdog Oscillator Frequency vs. VCC 124 122 FRC (kHz) -40 °C 120 25 °C 118 116 85 °C 114 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-383.ATmega1284P: Calibrated 8 MHz RC Oscillator vs. VCC 8.6 85 °C 8.4 25 °C FRC (MHz) 8.2 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-384.ATmega1284P: Calibrated 8 MHz RC Oscillator vs. Temperature 8.3 5.5 V 8.2 3.3 V 2.7 V FRC (MHz) 8.1 1.8 V 8 7.9 7.8 7.7 7.6 7.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-385.ATmega1284P: Calibrated 8 MHz RC Oscillator vs. OSCCAL Value 16 85 °C 25 °C -40 °C 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 28.8.12 Current Consumption of Peripheral Units Figure 28-386.ATmega1284P: ADC Current vs. VCC (AREF = AVCC) 280 -40 °C 25 °C 85 °C 260 240 ICC (uA) 220 200 180 160 140 120 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-387.ATmega1284P: Analog Comparator Current vs. VCC 85 -40 °C 25 °C 85 °C 75 ICC (uA) 65 55 45 35 25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-388.ATmega1284P: AREF External Reference Current vs. VCC 200 85 °C 25 °C -40 °C 180 ICC (uA) 160 140 120 100 80 60 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P ICC (uA) Figure 28-389.ATmega1284P: Brownout Detector Current vs. VCC 25 85 °C 23 25 °C 21 -40 °C 19 17 15 13 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 28-390.ATmega1284P: Programming Current vs. VCC 14 -40 °C 12 ICC (mA) 10 25 °C 8 85 °C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-391.ATmega1284P: Watchdog Timer Current vs. VCC 8.5 -40 °C 7.5 25 °C 85 °C ICC (uA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 28.8.13 Current Consumption in Reset and Reset Pulsewidth Figure 28-392.ATmega1284P: Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.1 5.5 V 5.0 V 0.08 ICC (mA) 4.5 V 4.0 V 0.06 3.3 V 0.04 2.7 V 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 550
164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 28-393.ATmega1284P: Reset Supply Current vs. Frequency (1 - 20 MHz) 1.6 5.5 V 1.4 5.0 V 1.2 4.5 V ICC (mA) 1 0.8 4.0 V 0.6 3.3 V 0.4 2.7 V 0.2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 28-394.ATmega1284P: Minimum Reset Pulsewidth vs. VCC 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 29.
PAGE 552
164A/164PA/324A/324PA/644A/644PA/1284/1284P Address (0xC0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190/205 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 236 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 233 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 2-wire Serial Interface Data Register TWA2
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Address Name (0x7E) DIDR0 (0x7D) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 260 - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 256 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 239 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High byte 258 259 (0x78) ADCL (0x77)
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1C (0x3C) Address EIFR Name - - - - - INTF2 INTF1 INTF0 69 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 70 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 160 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 139 0x15
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 30.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31. Ordering Information 31.1 ATmega164A Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega164A-AU ATmega164A-AUR(5) ATmega164A-PU ATmega164A-MU ATmega164A-MUR(5) ATmega164A-MCH(4) ATmega164A-MCHR(4)(5) ATmega164A-CU ATmega164A-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.2 ATmega164PA Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega164PA-AU ATmega164PA-AUR(5) ATmega164PA-PU ATmega164PA-MU ATmega164PA-MUR(5) ATmega164PA-MCH(4) ATmega164PA-MCHR(4)(5) ATmega164PA-CU ATmega164PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.3 ATmega324A Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega324A-AU ATmega324A-AUR(5) ATmega324A-PU ATmega324A-MU ATmega324A-MUR(5) ATmega324A-MCH(4) ATmega324A-MCHR(4)(5) ATmega324A-CU ATmega324A-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.4 ATmega324PA Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega324PA-AU ATmega324PA-AUR(5) ATmega324PA-PU ATmega324PA-MU ATmega324PA-MUR(5) ATmega324PA-MCH(4) ATmega324PA-MCHR(4)(5) ATmega324PA-CU ATmega324PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.5 ATmega644A Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega644A-AU ATmega644A-AUR(4) ATmega644A-PU ATmega644A-MU ATmega644A-MUR(4) 44A 44A 40P6 44M1 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.6 ATmega644PA Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega644PA-AU ATmega644PA-AUR(4) ATmega644PA-PU ATmega644PA-MU ATmega644PA-MUR(4) 44A 44A 40P6 44M1 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
PAGE 564
164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.7 ATmega1284 Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega1284-AU ATmega1284-AUR(4) ATmega1284-PU ATmega1284-MU ATmega1284-MUR(4) 44A 44A 40P6 44M1 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 31.8 ATmega1284P Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) Package(1) ATmega1284P-AU ATmega1284P-AUR(4) ATmega1284P-PU ATmega1284P-MU ATmega1284P-MUR(4) 44A 44A 40P6 44M1 44M1 Operational Range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 32. Packaging Information 32.1 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 32.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 32.3 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 32.4 44MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 D2 eT SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 C B5 B11 A6 A13 B10 B6 A12 L 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT – 0.70 – eR – 0.40 – K 0.45 – – L 0.30 0.35 0.40 y 0.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 32.5 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 SYMBOL A 2 3 4 5 b 6 7 e BOTTOM VIEW 49 - Ø0.35 ± 0.05 D1 E 3.90 BSC 4.90 5.00 E1 b NOTE 5.10 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 Package Drawing Contact: packagedrawings@atmel.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 33. Errata 33.1 33.1.1 Errata for ATmega164A Rev. E No known Errata. 33.2 33.2.1 Errata for ATmega164PA Rev. E No known Errata. 33.3 33.3.1 Errata for ATmega324A Rev. F No known Errata. 33.4 33.4.1 Errata for ATmega324PA Rev. F No known Errata. 33.5 33.5.1 Errata for ATmega644A Rev. F No known Errata. 33.6 33.6.1 Errata for ATmega644PA Rev. F No known Errata. 33.7 33.7.1 Errata for ATmega1284 Rev. B No known Errata. 33.8 33.8.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 34. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 34.1 Rev. 8272A - 01/10 1. Initial revision (Based on the ATmega164PA/324PA/644PA/1284P datasheet 8252G-AVR-11/09 and on the ATmega644 datasheet 2593N-AVR-09/09). 2.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 2 1.2Pinout - DRQFN for ATmega164A/164PA/324A/324PA ...........................................3 1.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 8.3Low Power Crystal Oscillator ...................................................................................33 8.4Full Swing Crystal Oscillator ....................................................................................34 8.5Low Frequency Crystal Oscillator ............................................................................35 8.6Calibrated Internal RC Oscillator .............................................................................
PAGE 575
164A/164PA/324A/324PA/644A/644PA/1284/1284P 12.2Register Description ..............................................................................................68 13 I/O-Ports .................................................................................................. 73 13.1Overview ...............................................................................................................73 13.2Ports as General Digital I/O ......................................................................
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 16.7Modes of Operation .............................................................................................145 16.8Timer/Counter Timing Diagrams .........................................................................149 16.9Asynchronous Operation of Timer/Counter2 .......................................................151 16.10Timer/Counter Prescaler ...................................................................................153 16.
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 20.22-wire Serial Interface Bus Definition ..................................................................208 20.3Data Transfer and Frame Format ........................................................................209 20.4Multi-master Bus Systems, Arbitration and Synchronization ...............................212 20.5Overview of the TWI Module ...............................................................................214 20.6Using the TWI ...............
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 24.2Overview .............................................................................................................267 24.3Data Registers .....................................................................................................268 24.4Boundary-scan Specific JTAG Instructions .........................................................269 24.5Boundary-scan Chain ........................................................................................
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164A/164PA/324A/324PA/644A/644PA/1284/1284P 27.6SPI Timing Characteristics ..................................................................................336 27.72-wire Serial Interface Characteristics .................................................................337 27.8ADC Characteristics ............................................................................................339 28 Typical Characteristics ........................................................................ 342 28.
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33.5Errata for ATmega644A ......................................................................................571 33.6Errata for ATmega644PA ....................................................................................571 33.7Errata for ATmega1284 .......................................................................................571 33.8Errata for ATmega1284P ....................................................................................571 34 Datasheet Revision History ..................
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.