Datasheet

86
2490R–AVR–02/2013
ATmega64(L)
•WR – Port G, Bit 0
WR
is the external data memory write control strobe.
Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals shown in
Figure 33 on page 71.
Table 46. Overriding Signals for Alternate Functions in PG4..PG1
Signal Name PG4/TOSC1 PG3/TOSC2 PG2/ALE PG1/RD
PUOE AS0 AS0 SRE SRE
PUOV 0 0 0 0
DDOE AS0 AS0 SRE SRE
DDOV 0 0 1 1
PVOE 0 0 SRE SRE
PVOV 0 0 ALE RD
DIEOE AS0 AS0 0 0
DIEOV 0 0 0 0
DI – – – –
AIO T/C0 OSC INPUT T/C0 OSC OUTPUT – –
Table 47. Overriding Signals for Alternate Functions in PG0
Signal Name PG0/WR
PUOE SRE
PUOV 0
DDOE SRE
DDOV 1
PVOE SRE
PVOV WR
DIEOE 0
DIEOV 0
DI –
AIO –