Datasheet

84
2490R–AVR–02/2013
ATmega64(L)
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5
.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal
Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK
PUOE JTAGEN JTAGEN JTAGEN JTAGEN
PUOV1011
DDOEJTAGENJTAGENJTAGENJTAGEN
DDOV 0 SHIFT_IR +
SHIFT_DR
00
PVOE 0 JTAGEN 0 0
PVOV0TDO00
DIEOEJTAGENJTAGENJTAGENJTAGEN
DIEOV0000
DI––––
AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5
INPUT
TCKADC4 INPUT