Datasheet

2490R–AVR–02/2013

ATmega64(L)

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

page 56 for details on operation of the Watchdog Timer.

Figure 27. Watchdog Reset During Operation

MCUCSR – MCU

Control and Status

(1)

The MCU Control and Status Register provides information on which reset source caused an

MCU Reset.

Note: 1. Only EXTRF and PORF are available in mega103 compatibility mode.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

Bit 76543210

0x34 (0x54)

JTD – – JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description