Datasheet

4
2490R–AVR–02/2013
ATmega64(L)
Analog Comparator Multiplexed Input 229
Analog to Digital Converter 230
Features 230
Operation 231
Starting a Conversion 232
Prescaling and Conversion Timing 233
Changing Channel or Reference Selection 236
ADC Noise Canceler 237
ADC Conversion Result 242
JTAG Interface and On-chip Debug System 248
Features 248
Overview 248
TAP – Test Access Port 248
TAP Controller 250
Using the Boundary -scan Chain 251
Using the On-chip Debug system 251
On-chip Debug Specific JTAG Instructions 252
On-chip Debug Related Register in I/O Memory 253
Using the JTAG Programming Capabilities 253
Bibliography 253
IEEE 1149.1 (JTAG) Boundary-scan 254
Features 254
System Overview 254
Data Registers 254
Boundary-scan Specific JTAG Instructions 256
Boundary-scan Related Register in I/O Memory 258
Boundary-scan Chain 258
ATmega64 Boundary-scan Order 270
Boundary-scan Description Language Files 276
Boot Loader Support – Read-While-Write Self-programming 277
Features 277
Application and Boot Loader Flash Sections 277
Read-While-Write and No Read-While-Write Flash Sections 277
Boot Loader Lock Bits 279
Entering the Boot Loader Program 281
Addressing the Flash During Self-programming 283
Self-programming the Flash 284
Memory Programming 290
Program and Data Memory Lock Bits 290
Fuse Bits 291
Signature Bytes 293