Datasheet

320
2490R–AVR–02/2013
ATmega64(L)
Virtual Flash Page
Load Register
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of
bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans-
ferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting
with the LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. This provides an efficient way to load the entire Flash page buffer before executing
Page Write.
Figure 153. Virtual Flash Page Load Register
Virtual Flash Page
Read Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automati-
cally transferred from the Flash data page byte-by-byte. The first eight cycles are used to
transfer the first byte to the internal Shift Register, and the bits that are shifted out during these
eight cycles should be ignored. Following this initialization, data are shifted out starting with the
LSB of the first instruction in the page and ending with the MSB of the last instruction in the
page. This provides an efficient way to read one full Flash page to verify programming.
TDI
TDO
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
STROBES
ADDRESS
State
Machine