Datasheet

304
2490R–AVR–02/2013
ATmega64(L)
Figure 146. Parallel Programming Timing, Reading Sequence (Within the Same Page) with
Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 144 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
reading operation.
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BHDV
t
OLDV
t
XLOL
t
OHDZ