Datasheet

30
2490R–AVR–02/2013
ATmega64(L)
Figure 13. External Data Memory Cycles without Wait State
(1)
(SRWn1 = 0 and SRWn0 =0)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal
or external).
Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal
or external).
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
XXXXX
XXXXXXXX
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. Addr.
DA7:0
Address DataPrev. Data XX
RD
DA7:0 (XMBK = 0)
DataPrev. Data Address
DataPrev. Data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)
T4