Datasheet

261
2490R–AVR–02/2013
ATmega64(L)
Figure 129. Additional Scan Signal for the Two-wire Interface
Scanning the RESET
Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 130 is
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 130. Observe-only Cell
Pxn
PUExn
ODxn
IDxn
TWIEN
OCxn
Slew-rate limited
SRC
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
From System Pin
To System Logic
FF1