Datasheet

191

2490R–AVR–02/2013

ATmega64(L)

• Bit 1 – RXB8n: Receive Data Bit 8

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

UCSRnC – USART

Control and Status

(1)

Note: 1. This register is not available in ATmega103 compatibility mode.

• Bit 7 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, this bit must be written to

zero when UCSRC is written.

• Bit 6 – UMSELn: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

• Bit 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.

If a mismatch is detected, the UPEn flag in UCSRnB will be set.

Bit 76 543 2 1 0

– UMSELn UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 1 1 0

Table 77. UMSEL Bit Settings

UMSELn Mode

0 Asynchronous Operation

1 Synchronous Operation

Table 78. UPM Bits Settings

UPMn1 UPMn0 Parity Mode

0 0 Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity