Datasheet

159
2490R–AVR–02/2013
ATmega64(L)
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page
153 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
TCNT2 –
Timer/Counter
Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
Table 67. Compare Output Mode, Phase Correct PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare
Match when downcounting.
1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare
Match when downcounting.
Table 68. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/counter stopped).
001clk
I/O
/(No prescaling)
010clk
I/O
/8 (From prescaler)
011clk
I/O
/64 (From prescaler)
100clk
I/O
/256 (From prescaler)
101clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on T2 pin. Clock on falling edge.
1 1 1 External clock source on T2 pin. Clock on rising edge.
Bit 76543210
0x24 (0x44) TCNT2[7:0] TCNT2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000