Datasheet

158
2490R–AVR–02/2013
ATmega64(L)
Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting. Table 65 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
Normal or CTC mode (non-PWM).
Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 152
for more details.
Table 67 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
PWM mode.
Table 64. Waveform Generation Mode Bit Description
(1)
Mode
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode
of Operation TOP
Update of
OCR2
TOV2 Flag
Set on
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR2 Immediate MAX
3 1 1 Fast PWM 0xFF BOTTOM MAX
Table 65. Compare Output Mode, non-PWM Mode
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
0 1 Toggle OC2 on Compare Match.
1 0 Clear OC2 on Compare Match.
1 1 Set OC2 on Compare Match.
Table 66. Compare Output Mode, Fast PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM,
(non-inverting mode).
1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM,
(inverting mode).