Datasheet

139
2490R–AVR–02/2013
ATmega64(L)
OCR1AH and OCR1AL
–Output Compare
Register 1 A
OCR1BH and OCR1BL
– Output Compare
Register 1 B
OCR1CH and OCR1CL
– Output Compare
Register 1 C
OCR3AH and OCR3AL
– Output Compare
Register 3 A
OCR3BH and OCR3BL
– Output Compare
Register 3 B
OCR3CH and OCR3CL
– Output Compare
Register 3 C
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See “Accessing 16-bit Registers” on page 115.
Bit 76543210
0x2B (0x4B) OCR1A[15:8] OCR1AH
0x2A (0x4A) OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x29 (0x49) OCR1B[15:8] OCR1BH
0x28 (0x48) OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x79) OCR1C[15:8] OCR1CH
(0x78) OCR1C[7:0] OCR1CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x87) OCR3A[15:8] OCR3AH
(0x86) OCR3A[7:0] OCR3AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x85) OCR3B[15:8] OCR3BH
(0x84) OCR3B[7:0] OCR3BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x83) OCR3C[15:8] OCR3CH
(0x82) OCR3C[7:0] OCR3CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000