Datasheet

135
2490R–AVR–02/2013
ATmega64(L)
Note: 1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. See “Phase Correct PWM Mode” on page 127. for more
details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 61. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 124.)
Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
(1)
COMnA1/
COMnB1/
COMnC1
COMnA0/
COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected.
0 1 WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match,
OCnB/OCnC disconnected (normal port operation).
Forr all other WGMn settings, normal port operation,
OCnA/OCnB/OCnC disconnected.
1 0 Clear OCnA/OCnB/OCnC on Compare Match when up-
counting. Set OCnA/OCnB/OCnC on Compare Match when
downcounting.
1 1 Set OCnA/OCnB/OCnC on Compare Match when up-counting.
Clear OCnA/OCnB/OCnC on Compare Match when
downcounting.