Datasheet

134
2490R–AVR–02/2013
ATmega64(L)
Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM
mode
Note: 1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the Compare Match is ignored, but the set or
clear is done at BOTTOM. See “Fast PWM Mode” on page 125. for more details.
Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor-
rect and frequency correct PWM mode.
Table 58. Compare Output Mode, non-PWM
COMnA1/
COMnB1/
COMnC1
COMnA0/
COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected.
0 1 Toggle OCnA/OCnB/OCnC on Compare Match.
1 0 Clear OCnA/OCnB/OCnC on Compare Match (Set output to
low level).
1 1 Set OCnA/OCnB/OCnC on Compare Match (Set output to high
level).
Table 59. Compare Output Mode, Fast PWM
(1)
COMnA1/
COMnB1/
COMnC0
COMnA0/
COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected.
0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match,
OCnB/OCnC disconnected (normal port operation).
For all other WGMn settings, normal port operation,
OCnA/OCnB/OCnC disconnected.
1 0 Clear OCnA/OCnB/OCnC on Compare Match, set
OCnA/OCnB/OCnC at BOTTOM (non-inverting mode).
1 1 Set OCnA/OCnB/OCnC on Compare Match, clear
OCnA/OCnB/OCnC at BOTTOM (inverting mode).