Datasheet
110
2490R–AVR–02/2013
ATmega64(L)
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
Timer/Counter
Prescaler
Figure 45. Prescaler for Timer/Counter0
The clock source for Timer/Counter0 is named clk
T0S
. clk
T0S
is by default connected to the main
system clock clk
OSC
. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked
from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When
AS0 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be con-
nected between the TOSC1 and TOSC2 pins to serve as an independent clock source for
Timer/Counter0. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an exter-
nal clock source to TOSC1 is not recommended.
For Timer/Counter0, the possible prescaled selections are: clk
T0S
/8, clk
T0S
/32, clk
T0S
/64,
clk
T0S
/128, clk
T0S
/256, and clk
T0S
/1024. Additionally, clk
T0S
as well as 0 (stop) may be selected.
Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to operate with a pre-
dictable prescaler.
10-BIT T/C PRESCALER
TIMER/COUNTER0 CLOCK SOURCE
clk
OSC
clk
T0S
TOSC1
AS0
CS00
CS01
CS02
clk
T0S
/8
clk
T0S
/64
clk
T0S
/128
clk
T0S
/1024
clk
T0S
/256
clk
T0S
/32
0
PSR0
Clear
clk
T0