Datasheet

106
2490R–AVR–02/2013
ATmega64(L)
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
56.
TCNT0 –
Timer/Counter
Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0 Register.
OCR0 – Output
Compare Register
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0 pin.
Table 56. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/counter stopped)
001clk
T0S
/(No prescaling)
010clk
T0S
/8 (From prescaler)
011clk
T0S
/32 (From prescaler)
100clk
T0S
/64 (From prescaler)
101clk
T0S
/128 (From prescaler)
110clk
T
0
S
/256 (From prescaler)
111clk
T
0
S
/1024 (From prescaler)
Bit 76543210
0x32 (0x52) TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x31 (0x51) OCR0[7:0] OCR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000