Datasheet

105
2490R–AVR–02/2013
ATmega64(L)
Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare
Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 99
for more details.
Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page
101 for more details.
Table 53. Compare Output Mode, non-PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Toggle OC0 on Compare Match.
1 0 Clear OC0 on Compare Match.
1 1 Set OC0 on Compare Match.
Table 54. Compare Output Mode, Fast PWM Mode
(1)
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
01Reserved
1 0 Clear OC0 on Compare Match, set OC0 at BOTTOM,
(non-inverting mode).
1 1 Set OC0 on Compare Match, clear OC0 at BOTTOM,
(inverting mode).
Table 55. Compare Output Mode, Phase Correct PWM Mode
(1)
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Reserved.
1 0 Clear OC0 on Compare Match when up-counting. Set OC0 on Compare
Match when downcounting.
1 1 Set OC0 on Compare Match when up-counting. Clear OC0 on Compare
Match when downcounting.