Features • High-performance, Low-power Atmel AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 64 Kbytes of In-System Reprogrammable Flash program memory – 2 Kbytes EEPROM – 4 Kbytes Internal SRAM – Write/Erase
ATmega64(L) Pin Configuration Figure 1.
ATmega64(L) Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 VCC GND PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS AVCC DATA DIR. REG.
ATmega64(L) The ATmega64 provides the following features: 64 Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillato
ATmega64(L) ATmega103 Compatibility Mode By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATmega64 are not available in this compatibility mode, these features are listed below: • One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available.
ATmega64(L) Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega64(L) RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 52. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting Oscillator amplifier. AVCC AVCC is the supply voltage pin for Port F and the A/D Converter.
ATmega64(L) Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega64(L) About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
ATmega64(L) AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
ATmega64(L) can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
ATmega64(L) Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega64(L) • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input.
ATmega64(L) X-, Y-, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
ATmega64(L) Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6.
ATmega64(L) When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag.
ATmega64(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega64(L) AVR Memories This section describes the different memories in the ATmega64. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega64 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega64 contains 64 Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega64(L) SRAM Data Memory The ATmega64 supports two different configurations for the SRAM data memory as listed in Table 1. Table 1. Memory Configurations Configuration Internal SRAM Data Memory External SRAM Data Memory Normal mode 4096 up to 64K ATmega103 compatibility mode 4000 up to 64K Figure 9 on page 20 shows how the ATmega64 SRAM Memory is organized.
ATmega64(L) The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and the 4,096 bytes of internal data SRAM in the ATmega64 are all accessible through all these addressing modes.
ATmega64(L) Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Access Instruction EEPROM Data Memory Next Instruction The ATmega64 contains 2 Kbytes of data EEPROM memory.
ATmega64(L) EEARH and EEARL – EEPROM Address Register Bit 15 14 13 12 11 10 9 8 0x1F (0x3F) – – – – – EEAR10 EEAR9 EEAR8 EEARH 0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write Initial Value R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 X X X X X X X X X X X • Bits 15..11 – Res: Reserved Bits These are reserved bits and will always read as zero.
ATmega64(L) • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
ATmega64(L) Table 2. EEPROM Programming Time(1) Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time 8448 8.4 ms EEPROM write (from CPU) Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings. The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega64(L) The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega64(L) Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
ATmega64(L) External Memory Interface Overview With all the features that the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are: • Four different wait-state settings (Including no wait-state). • Independent wait-state setting for different external memory sectors (configurable sector size).
ATmega64(L) ATmega103 Compatibility Using the External Memory Interface Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended I/O space. In ATmega103 compatibility mode, these registers are not available, and the features selected by these registers are not available. The device is still ATmega103 compatible, as these features did not exist in ATmega103.
ATmega64(L) Figure 12. External SRAM Connected to the AVR D[7:0] AD7:0 D ALE G AVR A15:8 RD WR Pull-up and Bus Keeper Q A[7:0] SRAM A[15:8] RD WR The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port Register to zero before entering sleep. The XMEM interface also provides a Bus Keeper on the AD7:0 lines.
ATmega64(L) Figure 13. External Data Memory Cycles without Wait State(1) (SRWn1 = 0 and SRWn0 =0) T1 T2 T3 T4 System Clock (CLKCPU ) ALE A15:8 Prev. addr. DA7:0 Prev. data Address DA7:0 (XMBK = 0) Prev. data Address DA7:0 (XMBK = 1) Prev. data Address XX Write Address Data WR XXXXX Data XXXXXXXX Read Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega64(L) Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. DA7:0 Prev. Data Address DA7:0 (XMBK = 0) Prev. Data Address DA7:0 (XMBK = 1) Prev. Data XX Write Address Data WR Address Read Data Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega64(L) XMEM Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions.
ATmega64(L) Table 3. Sector Limits with Different Settings of SRL2..
ATmega64(L) XMCRB – External Memory Control Register B Bit 7 6 5 4 3 2 1 0 XMBK – – – – XMM2 XMM1 XMM0 Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x6C) XMCRB • Bit 7 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the Bus Keeper.
ATmega64(L) Using all Locations of External Memory Smaller than 64 Kbytes Since the external memory is mapped after the internal memory as shown in Figure 11, the external memory is not addressed when addressing the first 4,352 bytes of data space. It may appear that the first 4,352 bytes of the external memory are inaccessible (external memory addresses 0x0000 to 0x10FF).
ATmega64(L) Using all 64Kbytes Locations of External Memory Since the external memory is mapped after the internal memory as shown in Figure 11, only 60 Kbytes of external memory is available by default (address space 0x0000 to 0x10FF is reserved for internal memory). However, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. This can be done by using the XMMn bits and controlled by software the most significant bits of the address.
ATmega64(L) System Clock and Clock Options Clock Systems and their Distribution Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 46. The clock systems are detailed below. Figure 18.
ATmega64(L) Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
ATmega64(L) XDIV – XTAL Divide Control Register The XTAL Divide Control Register is used to divide the source clock frequency by a number in the range 2 - 129. This feature can be used to decrease power consumption when the requirement for processing power is low.
ATmega64(L) Figure 19. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8. Table 8. Crystal Oscillator Operating Modes CKOPT CKSEL3..1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 1 101(1) 0.4 - 0.9 – 1 110 0.9 - 3.0 12 - 22 1 111 3.0 - 8.0 12 - 22 0 101, 110, 111 1.
ATmega64(L) Table 9. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
ATmega64(L) External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 20 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 20.
ATmega64(L) Calibrated Internal The calibrated internal RC Oscillator provides a fixed 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the RC Oscillator system clock by programming the CKSEL Fuses as shown in Table 13. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
ATmega64(L) non-zero values to this register will increase the frequency of the internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0 MHz.
ATmega64(L) Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF.
ATmega64(L) Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega64(L) Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega64(L) Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode.
ATmega64(L) Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
ATmega64(L) JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCSR.
ATmega64(L) System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the Reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega64(L) Figure 22. Reset Logic DATA BUS D Q L Q MCU Control and Status Register (MCUCSR) PORF BORF EXTRF WDRF JTRF PEN Pull-up Resistor Power-On Reset Circuit Brown-Out Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE FILTER JTAG Reset Register Reset Circuit COUNTER RESET RESET Watchdog Timer Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 19.
ATmega64(L) 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega64L and BODLEVEL=0 for ATmega64. BODLEVEL=1 is not applicable for ATmega64.
ATmega64(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 19) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 25.
ATmega64(L) Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 56 for details on operation of the Watchdog Timer. Figure 27. Watchdog Reset During Operation CC CK MCUCSR – MCU Control and Status Register(1) The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
ATmega64(L) • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Internal Voltage Reference ATmega64 features an internal bandgap reference.
ATmega64(L) Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON Safety Level WDT Initial State How to Disable the WDT How to Change Time-out M103C WDTON Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed sequence Unprogrammed Programmed 2 Enabled Always enabled Timed sequence Programmed Unprogrammed 0 Disabled Timed sequence No restriction Programmed Programmed 2 Enabled Always enabled Timed sequence Figure 28.
ATmega64(L) has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above.
ATmega64(L) The following code examples show one assembly and one C function for turning off the WDT. The examples assume that interrupts are controlled (for example, by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega64(L) Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. Safety Level 0 This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. The Time-out period can be changed at any time without restriction.
ATmega64(L) Interrupts Interrupt Vectors in ATmega64 This section describes the specifics of the interrupt handling as performed in ATmega64. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. Table 23. Reset and Interrupt Vectors Vector No.
ATmega64(L) Table 23. Reset and Interrupt Vectors (Continued) Vector No. Program Address(2) 32 Source Interrupt Definition 0x003E(3) USART1, UDRE USART1 Data Register Empty 33 0x0040(3) USART1, TX USART1, Tx Complete 34 (3) TWI Two-wire Serial Interface (3) SPM READY Store Program Memory Ready 0x0042 35 0x0044 Notes: 1.
ATmega64(L) 0x0022 jmp SPI_STC ; SPI Transfer Complete Handler 0x0024 jmp USART0_RXC ; USART0 RX Complete Handler 0x0026 jmp USART0_DRE ; USART0,UDR Empty Handler 0x0028 jmp USART0_TXC ; USART0 TX Complete Handler 0x002A jmp ADC ; ADC Conversion Complete Handler 0x002C jmp EE_RDY ; EEPROM Ready Handler 0x002E jmp ANA_COMP ; Analog Comparator Handler 0x0030 jmp TIM1_COMPC ; Timer1 CompareC Handler 0x0032 jmp TIM3_CAPT ; Timer3 Capture Handler 0x0034 jmp TIM3_COMPA ; Tim
ATmega64(L) When the BOOTRST Fuse is programmed and the Boot section size set to 8 Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x0044 jmp SPM_RDY ; Store Program Memory Ready Handler ; .
ATmega64(L) Loader section of the Flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-programming” on page 277 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2.
ATmega64(L) I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega64(L) Figure 30. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx Q Pxn D PORTxn Q CLR WPx DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: Configuring the Pin PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WPx: RRx: RPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
ATmega64(L) When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
ATmega64(L) Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATmega64(L) The following code example show how to set Port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega64(L) ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
ATmega64(L) Table 26. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega64(L) Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 27.
ATmega64(L) Table 29. Overriding Signals for Alternate Functions in PA3..
ATmega64(L) • OC1B, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • OC1A, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A.
ATmega64(L) Table 31. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/OC2/OC1C PB6/OC1B PB5/OC1A PB4/OC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 OC1B ENABLE OC1A ENABLE OC0 ENABLE OC1B OC1A OC0B PVOE OC2/OC1C ENABLE (1) (1) PVOV OC2/OC1C DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: 1. See “Output Compare Modulator (OCM1C2)” on page 161 for details. OC1C does not exist in ATmega103 compatibility mode.
ATmega64(L) Alternate Functions of Port C In ATmega103 compatibility mode, Port C is output only. The Port C has an alternate function as the address high byte for the External Memory Interface Table 33. Port C Pins Alternate Functions Port Pin Alternate Function PC7 A15 PC6 A14 PC5 A13 PC4 A12 PC3 A11 PC2 A10 PC1 A9 PC0 A8 Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in Figure 33 on page 71. Table 34.
ATmega64(L) Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1) Signal Name PC3/A11 PC2/A10 PC1/A9 PC0/A8 PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV 0 0 0 0 DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) DDOV 1 1 1 1 PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PVOV A11 A10 A9 A8 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: Alternate Functions of Port D 1.
ATmega64(L) • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt Source 3: The PD3 pin can serve as an External Interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1).
ATmega64(L) Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T2 PD6/T1 PD5/XCK1 PD4/ICP1 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 UMSEL1 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T2 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – – Table 38. Overriding Signals for Alternate Functions in PD3..
ATmega64(L) Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39. Table 39.
ATmega64(L) • AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data output.
ATmega64(L) Table 41. Overriding Signals for Alternate Functions in PE3..
ATmega64(L) • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5. TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 – Port F, Bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 - ADC0 – Port F, Bit 3..
ATmega64(L) Table 44. Overriding Signals for Alternate Functions in PF3..
ATmega64(L) • WR – Port G, Bit 0 WR is the external data memory write control strobe. Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals shown in Figure 33 on page 71. Table 46. Overriding Signals for Alternate Functions in PG4..
ATmega64(L) Register Description for I/O Ports PORTA – Port A Data Register DDRA – Port A Data Direction Register PINA – Port A Input Pins Address PORTB – Port B Data Register DDRB – Port B Data Direction Register PINB – Port B Input Pins Address PORTC – Port C Data Register DDRC – Port C Data Direction Register Bit 7 6 5 4 3 2 1 0 0x1B (0x3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0
ATmega64(L) PINC – Port C Input Pins Address Bit 7 6 5 4 3 2 1 0 0x13 (0x33) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINC In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-pull Zero Output. The port pins assumes their Initial Value, even if the clock is not running.
ATmega64(L) DDRF – Port F Data Direction Register PINF – Port F Input Pins Address Bit 7 6 5 4 3 2 1 0 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x61) Bit 7 6 5 4 3 2 1 0 0x00 (0x20) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A DDRF PINF Note that PORTF and DDRF Registers are not availab
ATmega64(L) External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4).
ATmega64(L) Table 48. Interrupt Sense Control(1) ISCn1 ISCn0 0 0 The low level of INTn generates an interrupt request. 0 1 Reserved 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: Description 1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register.
ATmega64(L) EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x39 (0x59) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bits 7..4 – INT7 - INT0: External Interrupt Request 7 - 0 Enable When an INT7 - INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled.
ATmega64(L) 8-bit Timer/Counter0 with PWM and Asynchronous Operation Timer/Counter0 is a general purpose, single-channel, 8-bit Timer/Counter module.
ATmega64(L) tive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See “Output Compare Unit” on page 95. for details.
ATmega64(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 35 shows a block diagram of the counter and its surrounding environment. Figure 35. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement.
ATmega64(L) Figure 36. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
ATmega64(L) Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37 shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega64(L) Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega64(L) value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output.
ATmega64(L) Figure 39. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin.
ATmega64(L) Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting.
ATmega64(L) The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega64(L) Figure 42. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 43 shows the setting of OCF0 in all modes except CTC mode. Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 44.
ATmega64(L) 8-bit Timer/Counter Register Description TCCR0 – Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x33 (0x53) FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM bits specify a non-PWM mode.
ATmega64(L) Table 53. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Toggle OC0 on Compare Match. 1 0 Clear OC0 on Compare Match. 1 1 Set OC0 on Compare Match. Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 54. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 0 0 Normal port operation, OC0 disconnected.
ATmega64(L) • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 56. Table 56.
ATmega64(L) Asynchronous Operation of the Timer/Counter ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 0x30 (0x50) – – – – AS0 TCN0UB OCR0UB TCR0UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O.
ATmega64(L) • The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and latched after two positive edges on TOSC1.
ATmega64(L) 1. Write any value to either of the registers OCR0 or TCCR0. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT0. • TIMSK – Timer/Counter Interrupt Mask Register During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag.
ATmega64(L) • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
ATmega64(L) SFIOR – Special Function IO Register Bit 7 6 5 4 3 2 1 0 0x20 (0x40) TSM – – – ACME PUD PSR0 PSR321 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding prescaler reset signals asserted.
ATmega64(L) 16-bit Timer/Counter (Timer/Counter 1 and Timer/Counter3 ) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement.
ATmega64(L) Figure 46. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVx (Int.Req.) Control Logic TCLK Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTx Tx = =0 OCFxA (Int.Req.) Waveform Generation = OCxA OCRxA OCFxB (Int.Req.) Fixed TOP Values Waveform Generation DATA BUS = OCxB OCRxB OCFxC (Int.Req.) Waveform Generation = OCRxC OCxC ( From Analog Comparator Ouput ) ICFx (Int.Req.
ATmega64(L) See “Output Compare Units” on page 121. The Compare Match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 227.
ATmega64(L) Accessing 16-bit Registers The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega64(L) The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega64(L) The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega64(L) Figure 47. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNTn by 1. Direction Select between increment and decrement. Clear Clear TCNTn (set all bits to zero). clkTn Timer/counter clock.
ATmega64(L) Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied.
ATmega64(L) Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 115. Input Capture Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit.
ATmega64(L) Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx flag is automatically cleared when the interrupt is executed.
ATmega64(L) automatically as the TCNTn – and ICRn Register). Therefore OCRnx is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written.
ATmega64(L) Figure 50. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega64(L) Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega64(L) An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
ATmega64(L) Figure 52. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value.
ATmega64(L) The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
ATmega64(L) Figure 53. Phase Correct PWM Mode, Timing Diagram OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM.
ATmega64(L) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
ATmega64(L) Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
ATmega64(L) output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures.
ATmega64(L) Figure 57. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value Figure 58 shows the same timing data, but with the prescaler enabled. Figure 58.
ATmega64(L) Initial Value 0 0 0 0 0 0 0 0 • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the Output Compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to.
ATmega64(L) Table 58. Compare Output Mode, non-PWM COMnA1/ COMnB1/ COMnC1 COMnA0/ COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 Toggle OCnA/OCnB/OCnC on Compare Match. 1 0 Clear OCnA/OCnB/OCnC on Compare Match (Set output to low level). 1 1 Set OCnA/OCnB/OCnC on Compare Match (Set output to high level). Description Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode Table 59.
ATmega64(L) Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/ COMnB1/ COMnC1 COMnA0/ COMnB0/ COMnC0 0 0 Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB/OCnC disconnected (normal port operation). Forr all other WGMn settings, normal port operation, OCnA/OCnB/OCnC disconnected. 1 0 Clear OCnA/OCnB/OCnC on Compare Match when upcounting. Set OCnA/OCnB/OCnC on Compare Match when downcounting.
ATmega64(L) Table 61.
ATmega64(L) • Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn).
ATmega64(L) TCCR3C – Timer/Counter3 Control Register C Bit 7 6 5 4 3 2 1 FOC3A FOC3B FOC3C – – – – – Read/Write W W W R R R R R Initial Value 0 0 0 0 0 0 0 0 (0x8C) 0 TCCR3C • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output Compare for Channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
ATmega64(L) OCR1AH and OCR1AL –Output Compare Register 1 A OCR1BH and OCR1BL – Output Compare Register 1 B OCR1CH and OCR1CL – Output Compare Register 1 C OCR3AH and OCR3AL – Output Compare Register 3 A OCR3BH and OCR3BL – Output Compare Register 3 B OCR3CH and OCR3CL – Output Compare Register 3 C Bit 7 6 5 4 3 0x2B (0x4B) OCR1A[15:8] 0x2A (0x4A) OCR1A[7:0] 2 1 0 OCR1AH OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2
ATmega64(L) ICR1H and ICR1L – Input Capture Register 1 ICR3H and ICR3L – Input Capture Register 3 Bit 7 6 5 4 3 0x27 (0x47) ICR1[15:8] 0x26 (0x46) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x81) ICR3[15:8] (0x80) ICR3[7:0] ICR3H ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value
ATmega64(L) • Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 61) is executed when the TOV1 flag, located in TIFR, is set.
ATmega64(L) TIFR – Timer/Counter Interrupt Flag Register(1) Bit 7 6 5 4 3 2 1 0 0x36 (0x56) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
ATmega64(L) • Bit 5 – ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capture 3 Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location.
ATmega64(L) Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers Timer/Counter3, Timer/Counter2 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all of the mentioned Timer/Counters. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega64(L) tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
ATmega64(L) 8-bit Timer/Counter2 with PWM Timer/Counter2 is a general purpose, single-channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 61.
ATmega64(L) ate a PWM or variable frequency output on the Output Compare pin (OC2). For details, see “Output Compare Unit” on page 148. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2.
ATmega64(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 62 shows a block diagram of the counter and its surroundings. Figure 62. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count TCNTn clear Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Select between increment and decrement.
ATmega64(L) Figure 63. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCn FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
ATmega64(L) Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting.
ATmega64(L) ter bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 157.
ATmega64(L) Figure 65. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega64(L) Figure 66. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
ATmega64(L) ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX.
ATmega64(L) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values.
ATmega64(L) Figure 69. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 70 shows the setting of OCF2 in all modes except CTC mode. Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
ATmega64(L) Figure 71.
ATmega64(L) Table 64. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2 TOV2 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
ATmega64(L) Table 67. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. Note: Description 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP.
ATmega64(L) OCR2 – Output Compare Register Bit 7 6 5 0x23 (0x43) 4 3 2 1 0 OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin.
ATmega64(L) Output Compare Modulator (OCM1C2) Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 112 and “8-bit Timer/Counter2 with PWM” on page 146.
ATmega64(L) Figure 73. Output Compare Modulator, Schematic COM21 COM20 Vcc COM1C1 COM1C0 Modulator 0 ( From Waveform Generator ) D 1 Q 1 OC1C Pin 0 ( From Waveform Generator ) D OC1C / OC2 / PB7 Q OC2 D Q D PORTB7 Q DDRB7 DATA BUS When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting.
ATmega64(L) SPI – Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64 and peripheral devices or between several AVR devices.
ATmega64(L) bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the buffer register for later use.
ATmega64(L) The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega64(L) The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega64(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega64(L) • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
ATmega64(L) SPSR – SPI Status Register Bit 7 6 5 4 3 2 1 0 0x0E (0x2E) SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
ATmega64(L) Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 70 and Table 71, as done below: Table 73.
ATmega64(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
ATmega64(L) The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
ATmega64(L) Figure 80. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
ATmega64(L) Table 74.
ATmega64(L) Figure 81. Synchronous Mode XCK Timing UCPOLn = 1 XCK RxD / TxD Sample UCPOLn = 0 XCK RxD / TxD Sample The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 81 shows, when UCPOLn is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
ATmega64(L) the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character Size (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select n (USBSn) bit. The receiver ignores the second stop bit.
ATmega64(L) Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRnH, r17 out UBRRnL, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega64(L) Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid– The USART den by the USART and given the function as the transmitter’s serial output. The baud rate, mode Transmitter of operation and frame format must be set up once before doing any transmissions.
ATmega64(L) Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers r17:r16.
ATmega64(L) Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
ATmega64(L) Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable n (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
ATmega64(L) Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDR. This rule applies to the FEn, DORn, and UPE status flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn, and UPEn bits, which all are stored in the FIFO, will change.
ATmega64(L) The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete n (RXCn) flag indicates if there are unread data present in the receive buffer.
ATmega64(L) Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the receiver will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed when the Receiver is disabled.
ATmega64(L) the figure. The Clock Recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition.
ATmega64(L) Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see Table 75) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
ATmega64(L) Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 76.
ATmega64(L) addressed. If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXBn = 0) is being transmitted.
ATmega64(L) load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO.
ATmega64(L) • Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. • Bit 0 – MPCMn: Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode.
ATmega64(L) • Bit 1 – RXB8n: Receive Data Bit 8 RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. • Bit 0 – TXB8n: Transmit Data Bit 8 TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn.
ATmega64(L) • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 79. USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 80.
ATmega64(L) UBRRnL and UBRRnH – USART Baud Rate Registers(1) Bit 15 14 13 12 – – – – 11 10 9 8 UBRRn[11:8] UBRRnH UBRRn[7:0] 7 Read/Write Initial Value Note: 6 5 UBRRnL 4 3 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1. UBRRH is not available in mega103 compatibility mode • Bit 15:12 – Reserved Bits These bits are reserved for future use.
ATmega64(L) Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz Baud Rate (bps) UBRRn Error UBRRn Errorn UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.
ATmega64(L) Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.
ATmega64(L) Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.
ATmega64(L) Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.
ATmega64(L) TWI – Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega64(L) Electrical Interconnection As depicted in Figure 86, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
ATmega64(L) Figure 88. START, REPEATED START, and STOP Conditions SDA SCL START Address Packet Format REPEATED START STOP START STOP All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
ATmega64(L) Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
ATmega64(L) Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
ATmega64(L) Figure 93. Arbitration between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from M SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega64(L) Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 94. All registers drawn in a thick line are accessible through the AVR data bus. Figure 94.
ATmega64(L) Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software.
ATmega64(L) TWI Register Description TWBR –TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x70) TWBR • Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
ATmega64(L) is detected, and then generates a new START condition to claim the Bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
ATmega64(L) • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 87. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 204. The value of TWPS1..0 is used in the equation.
ATmega64(L) • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
ATmega64(L) the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
ATmega64(L) Assembly code example(1) 1 ldi r16, (1<
ATmega64(L) Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega64(L) Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 96). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega64(L) This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition.
ATmega64(L) Figure 97.
ATmega64(L) Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a slave transmitter (see Figure 98). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega64(L) After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 89.
ATmega64(L) Figure 99.
ATmega64(L) Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see Figure 100). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 100. Data Transfer in Slave Receiver Mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER Device 3 ........
ATmega64(L) running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. Table 90.
ATmega64(L) Figure 101. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega64(L) Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 102). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 102. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........
ATmega64(L) In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one).
ATmega64(L) Figure 103. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega64(L) Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa.
ATmega64(L) • Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration.
ATmega64(L) Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega64(L) ACSR – Analog Comparator Control and Status Register Bit 7 6 5 4 3 2 1 0 0x08 (0x28) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode.
ATmega64(L) • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 93. Table 93. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
ATmega64(L) Analog to Digital Converter Features • • • • • • • • • • • • • • • • 10-bit Resolution 0.75 LSB Integral Non-linearity ±1.5 LSB Absolute Accuracy 13 µs - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Eight Multiplexed Single Ended Input Channels Seven Differential Input Channels Two Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0V - VCC ADC Input Voltage Range 2.7V - VCC Differential ADC Voltage Range Selectable 2.
ATmega64(L) Figure 108. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 MUX4 ADLAR REFS1 REFS0 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS AVCC PRESCALER START GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC INTERNAL 2.
ATmega64(L) The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
ATmega64(L) Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
ATmega64(L) The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
ATmega64(L) Figure 112. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 113.
ATmega64(L) Table 95. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Condition Auto Triggered conversions Normal conversions, differential Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
ATmega64(L) 1. When ADATE or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the interrupt flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value.
ATmega64(L) Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. 2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. 3.
ATmega64(L) Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. 2.
ATmega64(L) Figure 117. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 118.
ATmega64(L) Figure 119. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 120.
ATmega64(L) ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 97 on page 243 and Table 98 on page 244). 0x000 represents ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega64(L) Table 96. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 511/512 VREF/GAIN 0x1FF 511 VADCm + 510/512 VREF/GAIN 0x1FE 510 ... ... ... VADCm + 1/512 VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF/GAIN 0x3FF -1 ... ... ... VADCm - 511/512VREF/GAIN 0x201 -511 VADCm - VREF/GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result).
ATmega64(L) • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on page 246.
ATmega64(L) Table 98. Input Channel and Gain Selections (Continued) Positive Differential Input Negative Differential Input Gain 11010 ADC2 ADC2 1x 11011 ADC3 ADC2 1x 11100 ADC4 ADC2 1x 11101 ADC5 ADC2 1x MUX4..0 ADCSRA – ADC Control and Status Register A Single Ended Input 11110 1.
ATmega64(L) • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 99.
ATmega64(L) • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 242. ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x8E) – – – – – ADTS2 ADTS1 ADTS0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero.
ATmega64(L) JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega64(L) The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
ATmega64(L) Figure 124. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundaryscan circuitry, JTAG programming circuitry, or On-chip Debug system.
ATmega64(L) on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected data register. • Apply the TMS sequence 1, 1, 0 to reenter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
ATmega64(L) A debugger, like the AVR Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 252. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work.
ATmega64(L) On-chip Debug Related Register in I/O Memory OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 0x22 (0x42) MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega64(L) IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
ATmega64(L) controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 125 shows the structure of the Device Identification Register. Figure 125. The Format of the Device Identification Register LSB MSB Bit Device ID 31 28 27 12 11 1 0 Version Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1-bit Version Version is a 4-bit number identifying the revision of the component.
ATmega64(L) Reset Register The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states port pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega64(L) • IDCODE; 0x1 Update-DR: Data from the scan chain is applied to output pins. Optional JTAG instruction selecting the 32-bit ID-Register as data register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after Power-up. The active states are: SAMPLE_PRELOAD; 0x2 • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
ATmega64(L) Boundary-scan Related Register in I/O Memory MCUCSR – MCU Control and Status Register The MCU Control and Status Register contains control bits for general MCU functions, and provides information on which reset source caused an MCU Reset.
ATmega64(L) Figure 127.
ATmega64(L) Figure 128.
ATmega64(L) Figure 129. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn Pxn TWIEN SRC Slew-rate limited IDxn Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 130 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. To Next Cell ShiftDR FF1 0 D To System Logic From System Pin Figure 130.
ATmega64(L) Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 131 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
ATmega64(L) connecting the Oscillator pins from the scan path if not provided. The INTCAP Fuses are not supported in the scan-chain, so the boundary scan chain cannot make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed. Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 132. The Boundary-scan cell from Figure 133 is attached to each of these signals. The signals are described in Table 103.
ATmega64(L) To Next Cell ShiftDR EXTEST 0 1 0 D Q D Q 1 To Analog Circuitry/ To Digital Logic From Digital Logic/ From Analog Ciruitry Figure 133. General Boundary-scan Cell used for Signals for Comparator and ADC G From Previous Cell ClockDR UpdateDR Table 103.
ATmega64(L) Scanning the ADC Figure 134 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 130 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 134. Analog to Digital Converter VCCREN AREF IREFEN 2.56V Ref TO COMPARATOR PASSEN MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4 1.
ATmega64(L) Table 104.
ATmega64(L) Table 104. Boundary-scan Signals for the ADC(1) (Continued) Signal Name Direction as Seen from the ADC GNDEN Input Ground the negative input to comparator when true 0 0 HOLD Input Sample&Hold signal. Sample analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high.
ATmega64(L) Table 104. Boundary-scan Signals for the ADC(1) (Continued) Signal Name Direction as Seen from the ADC SCTEST Input Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4 0 0 ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high. 0 0 VCCREN Input Selects Vcc as the ACC reference voltage.
ATmega64(L) The recommended values from Table 104 are used unless other values are given in the algorithm in Table 105. Only the DAC and Port Pin values of the Scan-chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 105. Algorithm for Using the ADC(1) ADCEN DAC MUXEN HOLD PRECH PA3.
ATmega64(L) ATmega64 Boundary-scan Order Table 106 shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pinout order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of the other ports.
ATmega64(L) Table 106. ATmega64 Boundary-scan Order (Continued) Bit Number Signal Name Module 175 MUXEN_6 ADC 174 MUXEN_5 173 MUXEN_4 172 MUXEN_3 171 MUXEN_2 170 MUXEN_1 169 MUXEN_0 168 NEGSEL_2 167 NEGSEL_1 166 NEGSEL_0 165 PASSEN 164 PRECH 163 SCTEST 162 ST 161 VCCREN 160 PEN Programming Enable (Observe-only) 159 PE0.Data Port E 158 PE0.Control 157 PE0.Pullup_Enable 156 PE1.Data 155 PE1.Control 154 PE1.Pullup_Enable 153 PE2.Data 152 PE2.
ATmega64(L) Table 106. ATmega64 Boundary-scan Order (Continued) Bit Number Signal Name Module 139 PE6.Pullup_Enable Port E 138 PE7.Data 137 PE7.Control 136 PE7.Pullup_Enable 135 PB0.Data 134 PB0.Control 133 PB0.Pullup_Enable 132 PB1.Data 131 PB1.Control 130 PB1.Pullup_Enable 129 PB2.Data 128 PB2.Control 127 PB2.Pullup_Enable 126 PB3.Data 125 PB3.Control 124 PB3.Pullup_Enable 123 PB4.Data 122 PB4.Control 121 PB4.Pullup_Enable 120 PB5.Data 119 PB5.
ATmega64(L) Table 106. ATmega64 Boundary-scan Order (Continued) Bit Number Signal Name Module 103 RSTT 102 RSTHV Reset Logic (Observe-only) 101 EXTCLKEN 100 OSCON 99 RCOSCEN 98 OSC32EN 97 EXTCLK (XTAL1) 96 OSCCK 95 RCCK 94 OSC32CK 93 TWIEN TWI 92 PD0.Data Port D 91 PD0.Control 90 PD0.Pullup_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pullup_Enable 80 PD4.
ATmega64(L) Table 106. ATmega64 Boundary-scan Order (Continued) Bit Number Signal Name Module 67 PG0.Control Port G 66 PG0.Pullup_Enable 65 PG1.Data 64 PG1.Control 63 PG1.Pullup_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pullup_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pullup_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pullup_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pullup_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.
ATmega64(L) Table 106. ATmega64 Boundary-scan Order (Continued) Bit Number Signal Name Module 31 PA6.Control Port A 30 PA6.Pullup_Enable 29 PA5.Data 28 PA5.Control 27 PA5.Pullup_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pullup_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pullup_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pullup_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pullup_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pullup_Enable 11 PF3.Data 10 PF3.Control 9 PF3.
ATmega64(L) Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description.
ATmega64(L) Boot Loader Support – ReadWhile-Write Selfprogramming The Boot Loader Support provides a real Read-While-Write Self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega64(L) section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. RWW – Read-WhileWrite Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read.
ATmega64(L) Figure 136.
ATmega64(L) ory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted. Table 108. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section.
ATmega64(L) Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
ATmega64(L) • Bit 3 – BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Zpointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
ATmega64(L) Addressing the Flash During Selfprogramming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 123 on page 296), the Program Counter can be treated as having two different sections.
ATmega64(L) Self-programming the Flash The program memory is updated in a page-by-page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATmega64(L) Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 61.
ATmega64(L) Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
ATmega64(L) be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes.
ATmega64(L) ; read back and check, optional ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: lds temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable th
ATmega64(L) ATmega64 Boot Loader Parameters In Table 112 through Table 114, the parameters used in the description of the Self-programming are given. Table 112.
ATmega64(L) Memory Programming Program and Data Memory Lock Bits The ATmega64 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 116. The Lock bits can only be erased to “1” with the Chip Erase command. Table 115.
ATmega64(L) Table 116. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega64(L) Table 118. Fuse High Byte Fuse High Byte Bit no Description Default Value OCDEN 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(4) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable SPI Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega64(L) Latching of Fuses The fuse values are latched when the device enters Programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a 3-byte signature code which identifies the device.
ATmega64(L) Figure 138.
ATmega64(L) Table 120.
ATmega64(L) Table 123. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM Table 124. No. of Words in a Page and no. of Pages in the Flash Flash Size Page Size PCWORD No.
ATmega64(L) Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5V - 5.5V between VCC and GND, and wait at least 100 µs. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 121 on page 295 to “0000” and wait at least 100 ns. 4. Apply 11.5V - 12.5V to RESET.
ATmega64(L) Programming the Flash The Flash is organized in pages, see Table 123 on page 296. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
ATmega64(L) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 139.
ATmega64(L) Programming the EEPROM The EEPROM is organized in pages, see Table 124 on page 296. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 298 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
ATmega64(L) Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 298 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”.
ATmega64(L) Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 298 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase.
ATmega64(L) 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, (0x00 - 0x03). 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Characteristics Figure 144. Parallel Programming Timing, Including some General Timing Requirements t XLWL t XHXL XTAL1 t DVXH t XLDX Data & Contol (DATA, XA0/1, BS1, BS2) t PLBX t BVPH PAGEL t BVWL t WLBX t PHPL t WL WR WH t PLWL WLRL RDY/BSY t WLRH Figure 145.
ATmega64(L) Figure 146. Parallel Programming Timing, Reading Sequence (Within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLOL XTAL1 t BHDV BS1 t OLDV OE DATA t OHDZ ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 144 (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation.
ATmega64(L) Table 126. Parallel Programming Characteristics, VCC = 5V ±10% Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega64(L) SPI Serial Programming Pin Mapping Even though the SPI Programming interface re-uses the SPI I/O module, there is one important difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Programming mode as shown in Table 127. Table 127.
ATmega64(L) after SCK has been set to “0”. As an alternative to using the RESET signal, PEN can be held low during Power-on Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is important. If the programmer cannot guarantee that SCK is held low during Power-up, the PEN method cannot be used. The device must be powered down in order to commence normal operation when using this method. 2.
ATmega64(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
ATmega64(L) Table 129. SPI Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 xaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
ATmega64(L) Table 129. SPI Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Read Extendend Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-grammed, “1” = unprogrammed. See Table 119 on page 292 for details. Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 118 on page 292 for details.
ATmega64(L) Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.
ATmega64(L) Figure 149. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR AVR_RESET (0xC) 1 Exit1-IR 0 1 0 1 1 0 1 Update-IR 0 1 0 The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega64(L) PROG_ENABLE (0x4) PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16bit Programming Enable Register is selected as data register. The active states are the following: • Shift-DR: the Programming enable signature is shifted into the data register. • Update-DR: The programming enable signature is compared to the correct value, and programming mode is entered if the signature is valid.
ATmega64(L) Data Registers The data registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 311. The data registers relevant for programming operations are: • Reset Register Reset Register • Programming Enable Register • Programming Command Register • Virtual Flash Page Load Register • Virtual Flash Page Read Register The Reset Register is a Test Data Register used to reset the part during programming.
ATmega64(L) Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 130. The state sequence when shifting in the programming commands is illustrated in Figure 152. Figure 151.
ATmega64(L) Table 130. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega64(L) Table 130. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
ATmega64(L) Table 130. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
ATmega64(L) Figure 152.
ATmega64(L) Virtual Flash Page Load Register The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page.
ATmega64(L) Figure 154. Virtual Flash Page Read Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 130. Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 2.
ATmega64(L) Programming the Flash Before programming the Flash, a Chip Erase must be performed. See “Performing Chip Erase” on page 321. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address high byte using programming instruction 2b. 4. Load address low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7.
ATmega64(L) Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3.
ATmega64(L) Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data Low byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse Extended byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 1 on page 304). 6. Load data Low byte using programming instructions 6e.
ATmega64(L) Electrical Characteristics – TA = -40°C to 85°C Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega64(L) DC Characteristics TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Active 4 MHz, VCC = 3V (ATmega64L) 4.1 5 Active 8 MHz, VCC = 5V (ATmega64) 15.
ATmega64(L) External Clock Drive Waveforms Figure 155. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 131. External Clock Drive(1) VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.5 tCHCX High Time 50 25 tCLCX Low Time 50 25 tCLCH Rise Time 1.6 0.5 tCHCL Fall Time 1.6 0.
ATmega64(L) Two-wire Serial Interface Characteristics Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 156. Table 133. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Condition Min Max Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.
ATmega64(L) 5. This requirement applies to all ATmega64 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. Figure 156.
ATmega64(L) SPI Timing Characteristics See Figure 157 on page 330 and Figure 158 on page 331 for details. Table 134. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 72 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega64(L) Figure 158. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega64(L) ADC Characteristics Table 135. ADC Characteristics, Single Ended Channels, -40C – 85C Symbol Parameter Condition Resolution Single Ended Conversion 1.5 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz 3 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Noise Reduction mode 1.5 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Noise Reduction mode 3 Integral Non-Linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 0.
ATmega64(L) Table 136.
ATmega64(L) Table 136. ADC Characteristics, Differential Channels, -40C – 85C (Continued) Symbol Parameter Condition Min Typ Max Units 2.3 2.56 2.7 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M Notes: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V.
ATmega64(L) External Data Memory Timing Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state 8 MHz Oscillator Min Variable Oscillator Symbol Parameter Max 0 1/tCLCL Oscillator Frequency 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 2 tAVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 4 tAVLLC Address Valid C to ALE Low 57.5 0.
ATmega64(L) Table 139. External Data Memory Characteristics, 4.5V - 5.5V, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 15 tDVWH Data Valid to WR High 375 3.0tCLCL 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 325 3.0tCLCL-50 ns Table 140. External Data Memory Characteristics, 4.5V - 5.
ATmega64(L) Table 141. External Data Memory Characteristics, 2.7V - 5.5V, No Wait-state (Continued) 4 MHz Oscillator Symbol Parameter Min Max Variable Oscillator Min 0.5tCLCL-20 Max Unit (1) 13 tDVWL Data Setup to WR Low 105 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 15 tDVWH Data Valid to WR High 250 1.0tCLCL ns 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2.
ATmega64(L) Figure 159. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev. data Address 13 XX Data 14 16 6 Write 2 WR 3b DA7:0 (XMBK = 0) 11 9 Data 5 Read Address 10 8 12 RD Figure 160. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev.
ATmega64(L) Figure 161. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 162. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 3a DA7:0 Prev.
ATmega64(L) Electrical Characteristics – TA = -40°C to 105°C Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega64(L) DC Characteristics TA = -40°C to 105°C, VCC = 2.7V to 5.
ATmega64(L) Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega64(L) Figure 164. Active Supply Current vs. Frequency (1 MHz - 20 MHz) 45 5.5V 40 5.0V 35 Icc (mA) 30 25 4.5V 20 15 4.0V 10 3.6V 3.0V 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 165. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 2.8 85°C -40°C 2.6 2.4 Icc (mA) 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 166. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 5.5 85°C 25°C -40°C 5 Icc (mA) 4.5 4 3.5 3 2.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 167. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 11 25°C -40°C 85°C 10 Icc (mA) 9 8 7 6 5 4 3 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 168. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) -40°C 25°C 85°C 20 18 Icc (mA) 16 14 12 10 8 6 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 169. Active Supply Current vs. VCC (32 kHz External Oscillator) 130 120 25°C 110 Icc (μA) 100 90 80 70 60 50 40 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Idle Supply Current Figure 170. Idle Supply Current vs. Frequency (0.1 MHz - 1.0 MHz) Icc (mA) 1.4 5.5V 1.2 5.0V 1 4.5V 0.8 4.0V 3.6V 0.6 3.3V 0.4 2.7V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 171. Idle Supply Current vs. Frequency (1 MHz - 20 MHz) 25 5.5V 5.0V 20 Icc (mA) 4.5V 15 10 4.
ATmega64(L) Figure 172. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.6 85°C 25°C -40°C 1.4 Icc (mA) 1.2 1 0.8 0.6 0.4 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 173. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 3 85°C 25°C -40°C Icc (mA) 2.5 2 1.5 1 0.5 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 174. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 6 25°C 85°C -40°C 5.5 5 Icc (mA) 4.5 4 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 175. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) -40°C 25°C 85°C 11 10 9 Icc (mA) 8 7 6 5 4 3 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 176. Idle Supply Current vs. VCC (32 kHz External Oscillator) 80 75 25°C 70 65 Icc (μA) 60 55 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Power-Down Supply Current Figure 177. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 4 85°C 3.5 3 Icc (μA ) 2.5 2 -40°C 1.5 25°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 178. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 25 85°C 20 25°C -40°C Icc (μA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Power-Save Supply Current Figure 179. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled) 14 25°C 12 Icc (μA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Standby Supply Current Figure 180. Standby Supply Current vs. VCC 0.2 6 MHz Xtal 0.18 6 MHz Res 0.16 Icc (mA) 0.14 4 MHz Res 4 MHz Xtal 0.12 0.1 0.08 2 MHz Xtal 2 MHz Res 0.06 455 KHz Res 1 MHz Res 0.04 0.02 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 181. Standby Supply Current vs. VCC (CKOPT Programmed) 3 16 MHz Xtal 2.5 12 MHz Xtal Icc (mA) 2 6 MHz Xtal 1.5 4 MHz Xtal 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Pin Pull-up Figure 182. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 25°C 120 85°C -40°C IOP (μA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP(V) Figure 183. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 -40°C 70 25°C 60 85°C IOP (μA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega64(L) Figure 184. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 25°C -40°C 100 85°C IRESET (μA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Figure 185. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) cc 60 -40°C 25°C 50 85°C IRESET (μA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega64(L) Figure 186. PEN Pull-up Resistor Current vs. PEN Pin Voltage (VCC = 5V) 140 25°C -40°C 120 85°C IPEN (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VPEN (V) Figure 187. PEN Pull-up Resistor Current vs. PEN CC Pin Voltage (VCC = 2.7V) 80 25°C -40°C 70 85°C IPEN (μA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega64(L) Pin Driver Strength Figure 188. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 80 -40°C 25°C 70 85°C 60 IOH (mA) 50 40 30 20 10 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VOH (V) Figure 189. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) cc 30 25 -40°C 25°C 85°C IOH (mA) 20 15 10 5 0 0.5 1 1.5 2 2.
ATmega64(L) Figure 190. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 80 -40°C 70 25°C 60 85°C IOL (mA) 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 191. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) cc 30 -40°C 25°C 25 85°C IOL (mA) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega64(L) Pin Thresholds and Hysteresis Figure 192. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') 2.4 2.2 -40°C 85°C 25°C Threshold (V) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) (VIL, I/O Pin Read as '0') Figure 193. I/O Pin Input Threshold Voltage vs. V READ VIL. IO PINCC AS 0 1.5 -40°C 25°C 85°C 1.4 Threshold (V) 1.3 1.2 1.1 1 0.9 0.8 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 194. I/O Pin Input Hysteresis vs. VCC 0.8 -40°C 25°C 85°C Threshold (V) 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 195. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') 2.4 2.2 Threshold (V) 2 1.8 1.6 -40°C 1.4 25°C 1.2 85°C 1 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 196. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') 85°C 25°C -40°C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 4.5 5 5.5 V cc (V) Figure 197. Reset Input Pin Hysteresis vs. VCC 0.35 -40°C 0.3 Hysteresis (V) 0.25 0.2 0.15 25°C 0.1 0.05 85°C 0 2.5 3 3.
ATmega64(L) BOD Thresholds and Analog Comparator Offset Figure 198. BOD Thresholds vs. Temperature (BODLEVEL is 4.0V) 4 Rising Vcc Threshold (V) 3.95 3.9 3.85 Falling Vcc 3.8 3.75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Figure 199. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) 2.8 2.78 2.76 Rising Vcc Thres hold (V) 2.74 2.72 2.7 2.68 2.66 2.64 Falling Vcc 2.62 2.
ATmega64(L) Figure 200. Bandgap Voltage vs. VCC 1.275 85°C 1.27 Bandgap Voltage (V) -40°C 1.265 25°C 1.26 1.255 1.25 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Internal Oscillator Speed Figure 201. Watchdog Oscillator Frequency vs. VCC 1060 -40°C 25°C 1050 1040 85°C 1030 FRC (k Hz) 1020 1010 1000 990 980 970 960 950 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 202. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature 1.02 1 5.5V 5.0V FRC (MHz ) 0.98 4.5V 4.0V 3.6V 3.3V 0.96 0.94 2.7V 0.92 0.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Figure 203. Calibrated 1 MHz RC Oscillator Frequency vs. VCC 1.02 -40°C 25°C 1 85°C F RC (MHz ) 0.98 0.96 0.94 0.92 0.9 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 204. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value 1.5 25°C 1.4 1.3 1.2 FRC (MHz) 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 205. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature 2.05 2 5.5V 5.0V FRC (MHz) 1.95 4.5V 4.0V 3.6V 3.3V 1.9 1.85 2.7V 1.8 1.
ATmega64(L) Figure 206. Calibrated 2 MHz RC Oscillator Frequency vs. VCC 2.05 -40°C 25°C FRC (MHz) 2 85°C 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 207. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value 25°C 2.75 FRC (MHz) 2.25 1.75 1.25 0.
ATmega64(L) Figure 208. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature 4,1 4,05 4 5.5V 3,95 F RC (M Hz) 5.0V 3,9 4.5V 3,85 4.0V 3,8 3.6V 3,75 3.3V 3,7 2.7V 3,65 3,6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Figure 209. Calibrated 4 MHz RC Oscillator Frequency vs. VCC 4.1 -40°C 25°C 4.05 4 85°C FRC (MHz ) 3.95 3.9 3.85 3.8 3.75 3.7 3.65 3.6 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 210. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value 6.5 25°C 6 5.5 FRC (MHz) 5 4.5 4 3.5 3 2.5 2 1.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE Figure 211. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.3 8.1 7.9 5.5V 5.0V FRC (MHz) 7.7 4.5V 7.5 4.0V 7.3 3.6V 3.3V 7.1 6.9 2.7V 6.7 6.
ATmega64(L) Figure 212. Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.4 -40°C 8.2 25°C FRC (MHz) 8 85°C 7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 4.5 5 5.5 V cc (V) Figure 213. Calibrated 8 MHz RC Oscillator Frequency vs.
ATmega64(L) Current Consumption of Peripheral Units Figure 214. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. Vcc 16 14 -40°C 12 25°C Icc (μA) 10 8 6 85°C 4 2 0 2.5 3 3.5 4 4.5 5 5.5 V cc (V) Figure 215. ADC Current vs. VCC (ADC CLK = 50 kHz) 330 -40°C 310 25°C 290 Icc (μA) 270 85°C 250 230 210 190 170 150 130 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 216. Aref Current vs. VCC 170 85°C 25°C -40°C 160 150 Icc (μA) 140 130 120 110 100 90 80 70 2.5 3 3.5 4 4.5 5 5.5 V cc (V) Figure 217. Analog Comparator Current vs.
ATmega64(L) Figure 218. Programming Current vs. VCC 9 -40°C Icc (mA) 8 7 25°C 6 85°C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 V cc (V) Current Consumption in Reset and Reset Pulse width Figure 219. Reset Supply Current vs. VCC (0.1 MHz - 1.0 MHz, Excluding Current through the Reset Pull-up) 3.5 5.5V 3 5.0V ICC (m A) 2.5 4.5V 2 4.0V 1.5 3.6V 3.3V 2.7V 1 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega64(L) Figure 220. Reset Supply Current vs. VCC (1 MHz - 20 MHz, Excluding Current through the Reset Pull-up) Icc (mA) 40 35 5.5V 30 5.0V 25 4.5V 4.0V 20 3.6V 3.3V 15 2.7V 10 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 221. Minimum Reset Pulse Width vs. VCC 1200 Pulsewidth (ns) 1000 800 600 85°C 25°C 400 -40°C 200 0 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) ATmega64 Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega64(L) Figure 223. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 11 -40 °C 25 °C 85 °C 105 °C 10 9 Icc (mA) 8 7 6 5 4 3 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 224. Active Supply Current vs. VCC (Internal RC Oscillator, 2 kHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 2 MHz 5.5 105 °C 85 °C 25 °C -40 °C 5 Icc (mA) 4.5 4 3.5 3 2.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 225. Active Supply Current vs. VCC (Internal RC Oscillator, 1 kHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 2.8 105 °C 85 °C 25 °C -40 °C 2.6 2.4 Icc (mA) 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 226. Active Supply Current vs. VCC (Internal RC Oscillator, 1 kHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 2.8 105 °C 85 °C 25 °C -40 °C 2.6 2.4 Icc (mA) 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Idle Supply Current Figure 227. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 105 °C 85 °C 25 °C -40 °C 1.6 1.4 Icc (mA) 1.2 1 0.8 0.6 0.4 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 228. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 2 MHz 3 105 °C 85 °C 25 °C -40 °C 2.5 Icc (mA) 2 1.5 1 0.5 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 229. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 6 105 °C 85 °C 25 °C -40 °C 5.5 5 Icc (mA) 4.5 4 3.5 3 2.5 2 1.5 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 230. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 8 MHz -40 °C 25 °C 85 °C 105 °C 11 10 9 Icc (mA) 8 7 6 5 4 3 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Power-Down Supply Current Figure 231. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 9 105 °C 8 7 Icc (uA ) 6 5 4 85 °C 3 2 -40 °C 25 °C 1 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 232. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 30 25 105 °C Icc (uA) 20 85 °C 25 °C -40 °C 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Pin Pull-up Figure 233. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 25 °C -40 °C 140 120 85 °C 105 °C IOP (uA) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 234. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 25 °C -40 °C 70 60 85 °C 105 °C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega64(L) Figure 235. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 25 °C -40 °C 100 85 °C 105 °C IRESET (uA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Figure 236. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 85 °C 50 25 °C -40 °C 105 °C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega64(L) Pin Driver Strength Figure 237. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 80 -40 °C 25 °C 70 85 °C 60 105 °C IOH (mA) 50 40 30 20 10 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VOH (V) Figure 238. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 30 25 IOH (mA) 20 -40 °C 25 °C 85 °C 105 °C 15 10 5 0 0.5 1 1.5 2 2.
ATmega64(L) Figure 239. I/O Pin Sink Current vs. Output Voltage (Low Power Ports , VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 80 -40 °C 70 25 °C 60 85 °C 105 °C IOL (mA) 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 240. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 2,7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V IOL (mA) 30 -40 °C 25 25 °C 20 85 °C 105 °C 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega64(L) Pin Thresholds and Hysteresis Figure 241. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 2.4 2.2 -40 °C 25 °C 85 °C 105 °C Threshold (V) 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 242. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 1.5 -40 °C 25 °C 85 °C 105 °C 1.4 Thres hold (V ) 1.3 1.2 1.1 1 0.9 0.
ATmega64(L) Figure 243. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc 0.8 105 °C 85 °C 25 °C -40 °C Threshold (V) 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 244. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 2.4 2.2 Threshold (V) 2 1.8 1.6 -40 °C 1.4 25 °C 85 °C 1.2 105 °C 1 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Bod Thresholds and Analog Comparator Offset Figure 245. Bandgap Voltage vs Vcc) BANDGAP VOLTAGE vs. Vcc 1.25 Bandgap Voltage (V) 1.24 1.23 85 °C 105 °C -40 °C 1.22 1.21 1.2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Internal Oscillator Speed Figure 246. WDT Oscillator Frequency vs. Operativn Voltage WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1060 -40 °C 25 °C 1040 85 °C 105 °C F RC (kHz) 1020 1000 980 960 940 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 247. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc 4.1 -40 °C 25 °C 4.05 4 85 °C 3.95 105 °C F RC (MHz ) 3.9 3.85 3.8 3.75 3.7 3.65 3.6 3.55 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 248. 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc 8.4 -40 °C 8.2 25 °C 8 85 °C 105 °C F RC (MHz ) 7.8 7.6 7.4 7.2 7 6.8 6.6 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 249. 1 MHz RC Oscillator Frequency vs. Vcc CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. Vcc 1.02 -40 °C 25 °C 1 85 °C 105 °C FRC (MHz) 0.98 0.96 0.94 0.92 0.9 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 250. 1 kHz RC Oscillator Frequency vs. Oscillator CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE -40 °C 25 °C 85 °C 105 °C 1.5 1.4 1.3 1.2 F RC (MHz ) 1.1 1 0.9 0.8 0.7 0.6 0.5 0.
ATmega64(L) Figure 251. 2 MHz RC Oscillator Frequency vs. Vcc CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. Vcc 2.05 -40 °C 25 °C F RC (MHz ) 2 85 °C 105 °C 1.95 1.9 1.85 1.8 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 252. 2 MHz RC Oscillator Frequency vs Osccal CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C -40 °C 85 °C 105 °C 2.75 F RC (MHz ) 2.25 1.75 1.25 0.
ATmega64(L) Figure 253. 4 MHz RC Oscillator Frequency vs. Osccal CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 6.5 -40 °C 25 °C 85 °C 105 °C 6 5.5 F RC (MHz) 5 4.5 4 3.5 3 2.5 2 1.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Figure 254. 8 MHz RC Oscillator Frequency vs. Osccal CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
ATmega64(L) Current Consumption Of Peripheral Units Figure 255. 1 MHz Aref Current vs. VCC AREF CURRENT vs. Vcc ADC AT 1MHz 170 105 °C 85 °C 25 °C -40 °C 160 150 140 Icc (uA) 130 120 110 100 90 80 70 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 256. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs.
ATmega64(L) Figure 257. ADC Current vs. VCC ADC CURRENT vs. Vcc ADC AT 50KHz 330 -40 °C 310 25 °C 290 270 85 °C 105 °C Icc (uA) 250 230 210 190 170 150 130 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 258. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 90 105 °C 85 °C 80 Icc (uA) 70 25 °C 60 -40 °C 50 40 30 2.5 3 3.5 4 4.5 5 5.
ATmega64(L) Figure 259. Programming Current vs. VCC EEPROM WRITE CURRENT vs. Vcc Ext Clk 9 -40 °C Icc (mA) 8 7 25 °C 6 85 °C 5 105 °C 4 3 2 1 0 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Current Consumption In Reset and Reset Pulse Width Figure 260. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs.
ATmega64(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved – – – – – – – – ..
ATmega64(L) Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x60) Reserved – – – – – – – – Page 0x3F (0x5F) SREG I T H S V N Z C 12 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 14 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 14 0x3C (0x5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 39 0x3B (0x5B) Reserved – – – – – – – – 0x3A (0x5A) EICRB ISC71 ISC70 ISC61 ISC60
ATmega64(L) Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 (0x20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them.
ATmega64(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two R
ATmega64(L) Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
ATmega64(L) Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG H0 H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega64(L) Ordering Information Speed (MHz) 8 16 8 16 Note: Ordering Code(2) Package(1) 2.7 - 5.5 ATmega64L-8AU ATmega64L-8AUR(3) ATmega64L-8MU ATmega64L-8MUR(3) 64A 64A 64M1 64M1 4.5 - 5.5 ATmega64-16AU ATmega64-16AUR(3) ATmega64-16MU ATmega64-16MUR(3) 64A 64A 64M1 64M1 2.7 - 5.5 ATmega64L-8AN ATmega64L-8ANR(3) ATmega64L-8MN ATmega64L-8MNR(3) 64A 64A 64M1 64M1 4.5 - 5.
ATmega64(L) Packaging Information 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
ATmega64(L) 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b e BOTTOM VIEW Notes: Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 0.05 A1 – 0.02 b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.45 K 1.
ATmega64(L) Errata The revision letter in this section refers to the revision of the ATmega64 device. ATmega64, rev. A to C, E • • • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer Stabilizing time needed when changing XDIV Register Stabilizing time needed when changing OSCCAL Register IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1.
ATmega64(L) 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly.
ATmega64(L) Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1. Added “Electrical Characteristics – TA = -40°C to 105°C” on page 340. 2490Q-07/10 to 2. Added “ATmega64 Typical Characteristics – TA = -40°C to 105°C” on page 372. Rev. 2490R-02/13 3. Updated “Ordering Information” on page 398. 4. Changes from Rev. 1.
ATmega64(L) 3. Updated Table 52 on page 104, Table 54 on page 105, Table 59 on page 134, Table 61 on page 136, Table 64 on page 158, and Table 66 on page 158. 4. Updated “Errata” on page 401. Changes from Rev. 1. Updated Figure 2 on page 3. 2490J-03/05 to 2. Added “Resources” on page 8. Rev. 2490K-04/06 3. Added Addresses in Register Descriptions. 4. Updated “SPI – Serial Peripheral Interface” on page 163. 5. Updated Register- and bit names in “USART” on page 171. 6.
ATmega64(L) 9. Updated “Version” on page 255. 10. Updated “DC Characteristics” on page 325. 11. Updated “Typical Characteristics – TA = -40°C to 85°C” on page 342. 12. Updated features in“Analog to Digital Converter” on page 230 and Table 136 on page 333. 13. Updated “Ordering Information” on page 398. Changes from Rev. 1. Updated “Errata” on page 401. 2490F-12/03 to Rev. 2490G-03/04 Changes from Rev. 1. Updated “Calibrated Internal RC Oscillator” on page 43. 2490E-09/03 to Rev.
ATmega64(L) 7. Added note under "Filling the Temporary Buffer (Page Loading)" about writing to the EEPROM during an SPM page load. 8. Removed ADHSM completely. 9. Added note about masking out unused bits when reading the Program Counter in “Stack Pointer” on page 14. 10. Added section “EEPROM Write During Power-down Sleep Mode” on page 25. 11. Changed VHYST value to 120 in Table 19 on page 52. 12. Added information about conversion time for Differential mode with Auto Triggering on page 234. 13.
ATmega64(L) 10. Updated “TWI – Two-wire Serial Interface” on page 198. More details regarding use of the TWI Power-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit Rate Generator Unit” on page 204. Added the description at the end of “Address Match Unit” on page 205. 11. Updated Description of OSCCAL Calibration Byte.
ATmega64(L) Table of Contents Features 1 Pin Configuration 2 Disclaimer 2 Overview 3 Block Diagram 3 ATmega103 and ATmega64 Compatibility 4 Pin Descriptions 5 Resources 8 Data Retention 8 About Code Examples 9 AVR CPU Core 10 Introduction 10 Architectural Overview 10 ALU – Arithmetic Logic Unit 11 Status Register 12 General Purpose Register File 13 Stack Pointer 14 Instruction Execution Timing 14 Reset and Interrupt Handling 15 AVR Memories 18 In-System Reprogrammable Flash Program Memory 18 SRAM Data M
ATmega64(L) Idle Mode 47 ADC Noise Reduction Mode 47 Power-down Mode 47 Power-save Mode 47 Standby Mode 48 Extended Standby Mode 48 Minimizing Power Consumption 49 System Control and Reset 51 Internal Voltage Reference 56 Watchdog Timer 56 Timed Sequences for Changing the Configuration of the Watchdog Timer 60 Interrupts 61 Interrupt Vectors in ATmega64 61 I/O Ports 66 Introduction 66 Ports as General Digital I/O 66 Alternate Port Functions 71 Register Description for I/O Ports 87 External Interrupts 90
ATmega64(L) 16-bit Timer/Counter Register Description 132 Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers 144 8-bit Timer/Counter2 with PWM 146 Overview 146 Timer/Counter Clock Sources 147 Counter Unit 148 Output Compare Unit 148 Compare Match Output Unit 150 Modes of Operation 151 Timer/Counter Timing Diagrams 155 8-bit Timer/Counter Register Description 157 Output Compare Modulator (OCM1C2) 161 Overview 161 Description 161 SPI – Serial Peripheral Interface 163 SS Pin Functionality 167 Data
ATmega64(L) Analog Comparator Multiplexed Input 229 Analog to Digital Converter 230 Features 230 Operation 231 Starting a Conversion 232 Prescaling and Conversion Timing 233 Changing Channel or Reference Selection 236 ADC Noise Canceler 237 ADC Conversion Result 242 JTAG Interface and On-chip Debug System 248 Features 248 Overview 248 TAP – Test Access Port 248 TAP Controller 250 Using the Boundary -scan Chain 251 Using the On-chip Debug system 251 On-chip Debug Specific JTAG Instructions 252 On-chip Debu
ATmega64(L) Calibration Byte 293 Parallel Programming Parameters, Pin Mapping, and Commands 293 Parallel Programming 297 Serial Downloading 305 SPI Serial Programming Pin Mapping 306 Programming Via the JTAG Interface 311 Electrical Characteristics – TA = -40°C to 85°C 325 Absolute Maximum Ratings* 325 DC Characteristics 325 External Clock Drive Waveforms 327 External Clock Drive 327 Two-wire Serial Interface Characteristics 328 SPI Timing Characteristics 330 ADC Characteristics 332 External Data Memory Ti
ATmega64(L) Changes from Rev. 2490J-03/05 to Rev. 2490K-04/06 404 Changes from Rev. 2490I-10/04 to Rev. 2490J-03/05 404 Changes from Rev. 2490H-10/04 to Rev. 2490I-11/04 404 Changes from Rev. 2490G-03/04 to Rev. 2490H-10/04 404 Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 405 Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 405 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 405 Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03 405 Changes from Rev. 2490B-09/02 to Rev.
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