Datasheet

14
2545TS–AVR–05/11
ATmega48/88/168
BRIE k Branch if interrupt enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if interrupt disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set bit in I/O register I/O(P,b) ← 1None2
CBI P,b Clear bit in I/O register I/O(P,b) ← 0None2
LSL Rd Logical shift left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z, C, N, V 1
LSR Rd Logical shift right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z, C, N, V 1
ROL Rd Rotate left through carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z, C, N, V 1
ROR Rd Rotate right through carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z, C, N, V 1
ASR Rd Arithmetic shift right Rd(n) ← Rd(n+1), n=0..6 Z, C, N, V 1
SWAP Rd Swap nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag set SREG(s) ← 1 SREG(s) 1
BCLR s Flag clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit store from register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to register Rd(b) ← TNone1
SEC Set carry C ← 1C1
CLC Clear carry C ← 0 C 1
SEN Set negative flag N ← 1N1
CLN Clear negative flag N ← 0 N 1
SEZ Set zero flag Z ← 1Z1
CLZ Clear zero flag Z ← 0 Z 1
SEI Global interrupt enable I ← 1I1
CLI Global interrupt disable I ← 0 I 1
SES Set signed test flag S ← 1S1
CLS Clear signed test flag S ← 0 S 1
SEV Set Twos complement overflow V ← 1V1
CLV Clear Twos complement overflow V ← 0 V 1
SET Set T in SREG T ← 1T1
CLT Clear T in SREG T ← 0 T 1
SEH Set half carry flag in SREG H ← 1H1
CLH Clear half carry flag in SREG H ← 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move between registers Rd ← Rr None 1
MOVW Rd, Rr Copy register Word
Rd+1:Rd ← Rr+1:Rr
None 1
LDI Rd, K Load immediate Rd ← KNone1
LD Rd, X Load indirect Rd ← (X) None 2
LD Rd, X+ Load indirect and post-inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load indirect and pre-dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load indirect Rd ← (Y) None 2
LD Rd, Y+ Load indirect and post-inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load indirect and pre-dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load indirect with displacement Rd ← (Y + q) None 2
LD Rd, Z Load indirect Rd ← (Z) None 2
LD Rd, Z+ Load indirect and post-inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load indirect and pre-dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load indirect with displacement Rd ← (Z + q) None 2
LDS Rd, k Load direct from SRAM Rd ← (k) None 2
ST X, Rr Store indirect (X) ← Rr None 2
ST X+, Rr Store indirect and post-inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store indirect and pre-dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store indirect (Y) ← Rr None 2
ST Y+, Rr Store indirect and post-inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store indirect and pre-dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store indirect with displacement (Y + q) ← Rr None 2
ST Z, Rr Store indirect (Z) ← Rr None 2
ST Z+, Rr Store indirect and post-inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store indirect and pre-dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store indirect with displacement (Z + q) ← Rr None 2
STS k, Rr Store direct to SRAM (k) ← Rr None 2
LPM Load program memory R0 ← (Z) None 3
LPM Rd, Z Load program memory Rd ← (Z) None 3
LPM Rd, Z+ Load program memory and post-inc Rd ← (Z), Z ← Z+1 None 3
SPM Store program memory (Z) ← R1:R0 None -
IN Rd, P In port Rd ← PNone1
OUT P, Rr Out port P ← Rr None 1
PUSH Rr Push register on stack STACK ← Rr None 2
Mnemonics Operands Description Operation Flags #Clocks