Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 32 (5x5) 8-Bit 10 MHz I/O number 23

Features

• High performance, low power Atmel

AVR

8-bit microcontroller

• Advanced RISC architecture

– 131 powerful instructions – most single clock cycle execution

– 32 × 8 general purpose working registers

– Fully static operation

– Up to 20 MIPS throughput at 20MHz

– On-chip 2-cycle multiplier

• High endurance non-volatile memory segments

– 4/8/16 Kbytes of in-system self-programmable flash program memory

– 256/512/512 bytes EEPROM

– 512/1K/1Kbytes internal SRAM

– Write/erase cyles: 10,000 flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

()

– Optional boot code section with independent lock bits

In-system programming by on-chip boot program

True read-while-write operation

– Programming lock for software security

• QTouch

library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

• Peripheral features

– Two 8-bit timer/counters with separate prescaler and compare mode

– One 16-bit timer/counter with separate prescaler, compare mode, and capture mode

– Real time counter with separate oscillator

– Six PWM channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

– 6-channel 10-bit ADC in PDIP Package

– Programmable serial USART

– Master/slave SPI serial interface

– Byte-oriented 2-wire serial interface (Philips I

C compatible)

– Programmable watchdog timer with separate on-chip oscillator

– On-chip analog comparator

– Interrupt and wake-up on pin change

• Special microcontroller features

– DebugWIRE on-chip debug system

– Power-on reset and programmable brown-out detection

– Internal calibrated oscillator

– External and internal interrupt sources

– Five sleep modes: Idle, ADC noise reduction, power-save, power-down, and standby

• I/O and packages

– 23 programmable I/O lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating voltage:

– 1.8V - 5.5V for Atmel ATmega48V/88V/168V

– 2.7V - 5.5V for Atmel ATmega48/88/168

• Temperature range:

–-40

°C to 85°C

• Speed grade:

– ATmega48V/88V/168V: 0 - 4MHz @ 1.8V - 5.5V, 0 - 10MHz @ 2.7V - 5.5V

– ATmega48/88/168: 0 - 10MHz @ 2.7V - 5.5V, 0 - 20MHz @ 4.5V - 5.5V

• Low power consumption

– Active mode:

250µA at 1MHz, 1.8V

15µA at 32kHz, 1.8V (including oscillator)

– Power-down mode:

0.1µA at 1.8V

Note: 1. See “Data Retention” on page 7 for details.

8-bit Atmel

Microcontroller

with 4/8/16K

Bytes In-System

Programmable

Flash

ATmega48/V

ATmega88/V

ATmega168/V

Summary

Rev. 2545TS–AVR–05/11

Summary of content (36 pages)

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Features • High performance, low power Atmel® AVR® 8-bit microcontroller • Advanced RISC architecture • • • • • • • • • – 131 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 20 MIPS throughput at 20MHz – On-chip 2-cycle multiplier High endurance non-volatile memory segments – 4/8/16 Kbytes of in-system self-programmable flash program memory – 256/512/512 bytes EEPROM – 512/1K/1Kbytes internal SRAM – Write/erase cyles
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1. Pin configurations Figure 1-1.
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ATmega48/88/168 1.1 1.1.1 Pin descriptions VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
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resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in “Alternate functions of port D” on page 83. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC.
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ATmega48/88/168 2. Overview The Atmel ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block diagram Block Diagram GND Figure 2-1. VCC 2.
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architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega48/88/168 ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash.
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3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device.
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ATmega48/88/168 7.
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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBF) Reserved – – – – – – – – – 10 Page (0xBE) Reserved – – – – – – – (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 238 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 235 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 238 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 237 (0xB8) TWBR (0xB7) Reserved – (0xB6) ASSR – (0xB5) R
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ATmega48/88/168 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7D) Reserved – – – – – – – – Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 254 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 257 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 255 (0x79) ADCH ADC data register high byte (0x78) ADCL ADC data register low byte (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75)
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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 157 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 135 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33) Reserv
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ATmega48/88/168 8.
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Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if interrupt enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if interrupt disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set bit in I/O register I/O(P,b) ← 1 None 2 CBI P,b Clear bit in I/O register I/O(P,b) ← 0 None 2 LSL Rd Logical shift left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z, C, N, V 1 LSR Rd Logical shift right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z, C,
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ATmega48/88/168 Mnemonics POP Operands Rd Description Pop register from stack Operation Rd ← STACK Flags #Clocks None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No operation SLEEP Sleep (See specific descr. for sleep function) None 1 WDR BREAK Watchdog reset Break (See specific descr. for WDR/timer) For on-chip debug only None None 1 N/A Note: 1. These instructions are only available in Atmel ATmega168.
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9. Ordering information 9.1 Atmel ATmega48 Speed (MHz) Power supply Ordering code(2) Package(1) (5) 10(3) 20(3) Note: Operational range 1.8V - 5.5V ATmega48V-10AUR ATmega48V-10MUR(5) ATmega48V-10AU ATmega48V-10MMU ATmega48V-10MMUR(5) ATmega48V-10MMH(4) ATmega48V-10MMHR(4)(5) ATmega48V-10MU ATmega48V-10PU 32A 32M1-A 32A 28M1 28M1 28M1 28M1 32M1-A 28P3 Industrial (-40°C to 85°C) 2.7V - 5.
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ATmega48/88/168 9.2 Atmel ATmega88 Speed (MHz) Power supply Ordering code(2) Package(1) (4) 10(3) 20(3) Note: Operational range 1.8V - 5.5V ATmega88V-10AUR ATmega88V-10MUR(4) ATmega88V-10AU ATmega88V-10MU ATmega88V-10PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 2.7V - 5.5V ATmega88-20AUR(4) ATmega88-20MUR(4) ATmega88-20AU ATmega88-20MU ATmega88-20PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
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9.3 Atmel ATmega168 Speed (MHz)(3) Power supply Ordering code(2) Package(1) (4) 10 20 Note: Operational range 1.8V - 5.5V ATmega168V-10AUR ATmega168V-10MUR(4) ATmega168V-10AU ATmega168V-10MU ATmega168V-10PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 2.7V - 5.5V ATmega168-20AUR(4) ATmega168-20MUR(4) ATmega168-20AU ATmega168-20MU ATmega168-20PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
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ATmega48/88/168 10. Packaging Information 10.1 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum.
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10.2 28M1 D C 1 2 Pin 1 ID 3 E SIDE VIEW A1 TOP VIEW A y D2 K 1 0.45 2 R 0.20 3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C L e 0.4 Ref (4x) Note: 0.20 REF D 3.95 4.00 4.05 D2 2.35 2.40 2.45 E 3.95 4.00 4.05 E2 2.35 2.40 2.45 e BOTTOM VIEW The terminal #1 ID is a Laser-marked Feature. NOTE 0.45 L 0.35 0.40 0.45 y 0.00 – 0.08 K 0.
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ATmega48/88/168 10.3 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig.
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10.4 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 B A1 (4 PLACES) e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF SYMBOL eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN NOM MAX A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
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ATmega48/88/168 11. Errata 11.1 Errata Atmel ATmega48 The revision letter in this section refers to the revision of the ATmega48 device. 11.1.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
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11.1.4 Rev A • • • • • • • Part may hang in reset Wrong values read after erase only operation Watchdog timer interrupt disabled Start-up time with crystal oscillator is higher than expected High power consumption in power-down with external clock Asynchronous oscillator does not stop in power-down Interrupts may be lost when writing the timer registers in the asynchronous timer 1.
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ATmega48/88/168 3. Watchdog timer interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly.
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11.2 Errata Atmel ATmega88 The revision letter in this section refers to the revision of the ATmega88 device. 11.2.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
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ATmega48/88/168 Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active. If an external reset push button is used, the reset start-up time should be selected such that the reset line is fully debounced during the start-up time. The second case can be avoided by not using the system clock prescaler. The third case occurs during In-System programming only. It is most frequently seen when using the internal RC at maximum frequency.
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- A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active.
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ATmega48/88/168 - Two succeeding resets are applied where the second reset occurs in the 10ns window before the device is out of the reset-state caused by the first reset. - A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device.
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12. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 12.1 Rev. 2545T-04/11 1. 2. 3. 4. 12.2 Rev. 2545S-07/10 1. 2. 12.3 2. Removed the heading “About”. The subsections of this sectionis now separate sections, “Resources”, “Data Retention” and “About Code Examples” Updated “Ordering information” on page 15. Rev. 2545P-02/09 1.
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ATmega48/88/168 12.6 Rev. 2545O-02/09 1. 2. 12.7 Rev. 2545N-01/09 1. 2. 3. 4. 5. 6. 7. 12.8 Updated “Features” on page 1 and added the note “Not recommended for new designs”. Merged the sections Resources, Data Retention and About Code Examples under one common section, “Resources” on page 7. Updated Figure 8-4 on page 34. Updated “System clock prescaler” on page 35. Updated “Alternate functions of port B” on page 77. Added section “” on page 306. Updated “Pin thresholds and hysteresis” on page 329.
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12.11 Rev. 2545J-12/06 1. 2. 3. 4. Updated “Features” on page 1. Updated Table 1-1 on page 2. Updated “Ordering information” on page 15. Updated “Packaging Information” on page 18. 12.12 Rev. 2545I-11/06 1. 2. 3. Updated “Features” on page 1. Updated Features in “2-wire serial interface” on page 208. Fixed typos in Table 28-3 on page 306. 12.13 Rev. 2545H-10/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Updated typos. Updated “Features” on page 1.
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ATmega48/88/168 8. 9. 10. 11. 12. 13. 14. 15. 16. 17 18. 19. 20. Updated “Fast PWM mode” on page 120. Updated “Asynchronous operation of Timer/Counter2” on page 150. Updated “SPI – Serial peripheral interface” on page 160. Updated “UCSRnA – USART MSPIM control and status register n A” on page 205. Updated note in “Bit rate generator unit” on page 215. Updated “Bit 6 – ACBG: Analog comparator bandgap select” on page 241. Updated Features in “Analog-to-digital converter” on page 243.
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12.17 Rev. 2545D-07/04 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Updated instructions used with WDTCSR in relevant code examples. Updated Table 8-5 on page 30, Table 28-4 on page 306, Table 26-9 on page 281, and Table 26-11 on page 282. Updated “System clock prescaler” on page 35. Moved “TIMSK2 – Timer/Counter2 interrupt mask register” on page 157 and “TIFR2 – Timer/Counter2 interrupt flag register” on page 157 to “Register description” on page 152.
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10. 11. 12. Renamed the following bits: - SPMEN to SELFPRGEN - PSR2 to PSRASY - PSR10 to PSRSYNC - Watchdog Reset to Watchdog System Reset Updated C code examples containing old IAR syntax. Updated BLBSET description in “SPMCSR – Store program memory control and status register” on page 282.
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.