Datasheet

Symbol Parameter Min. Max Units
t
PLWL
PAGEL Low to WR Low 67 - ns
t
BVWL
BS1 Valid to WR Low 67 - ns
t
WLWH
WR Pulse Width Low 150 - ns
t
WLRL
WR Low to RDY/BSY Low 0 1 μs
t
WLRH
WR Low to RDY/BSY High
(1)
3.2 3.4 ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
(2)
9.8 10.5 ms
t
XLOL
XTAL1 Low to OE Low 0 - ns
t
BVDV
BS1 Valid to DATA valid 0 350 ns
t
OLDV
OE Low to DATA Valid - 350 ns
t
OHDZ
OE High to DATA Tri-stated - 250 ns
Note:
1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
Figure 33-6. Parallel Programming Timing, Including some General Timing Requirements
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
Figure 33-7. Parallel Programming Timing, Loading Sequence with Timing Requirements
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
ATmega48PA/88PA/168PA
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 396