Datasheet

Table 32-3. Lock Bit Protection - BLB0 Mode
(1)(2)
BLB0
Mode
BLB02 BLB01
1 1 1 No restrictions for SPM or Load Program Memory (LPM) instruction
accessing the application section.
2 1 0 SPM is not allowed to write to the application section.
3 0 0 SPM is not allowed to write to the application section, and LPM executing
from the boot loader section is not allowed to read from the application
section. If interrupt vectors are placed in the boot loader section, interrupts
are disabled while executing from the application section.
4 0 1 LPM executing from the boot loader section is not allowed to read from the
application section. If interrupt vectors are placed in the boot loader
section, interrupts are disabled while executing from the application
section.
Table 32-4. Lock Bit Protection - BLB1 Mode
(1)(2)
BLB1
Mode
BLB12 BLB11
1 1 1 No restrictions for SPM or LPM accessing the boot loader section.
2 1 0 SPM is not allowed to write to the boot loader section.
3 0 0 SPM is not allowed to write to the boot loader section, and LPM executing
from the application section is not allowed to read from the boot loader
section. If interrupt vectors are placed in the application section, interrupts
are disabled while executing from the boot loader section.
4 0 1 LPM executing from the application section is not allowed to read from the
boot loader section. If interrupt vectors are placed in the application
section, interrupts are disabled while executing from the boot loader
section.
Note:
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. '1' means unprogrammed; '0' means programmed.
32.2 Fuse Bits
The device has three Fuse bytes. The following tables describe briefly the functionality of all the fuses
and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are
programmed.
ATmega48PA/88PA/168PA
Memory Programming (MEMPROG)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 365