Datasheet

Figure 11-4. The Parallel Instruction Fetches and Instruction Executions

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU

operation using two register operands is executed and the result is stored back to the destination register.

Figure 11-5. Single Cycle ALU Operation

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

11.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset vector

each have a separate program vector in the program memory space. All interrupts are assigned

individual enable bits, which must be written logic one together with the global interrupt enable bit in the

Status register in order to enable the interrupt. Depending on the program counter value, interrupts may

be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves

software security.

The lowest addresses in the program memory space are by default defined as the Reset and interrupt

vectors. They have determined priority levels: The lower the address the higher is the priority level.

RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors

can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register

(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the

BOOTRST Fuse.

When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The

user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then

interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction

– RETI – is executed.

There are basically two types of interrupts:

The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program

counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and

ATmega48PA/88PA/168PA

AVR CPU Core

Datasheet Complete

DS40002011A-page 36