Datasheet

11.5.1 Stack Pointer Register Low and High byte
Name:  SPL and SPH
Offset:  0x5D
Reset:  0x4FF
Property:  When addressing I/O registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit 15 14 13 12 11 10 9 8
SP10 SP9 SP8
Access
R R R R R RW RW RW
Reset 0 0 0 0 0 1 0 0
Bit 7 6 5 4 3 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access
RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 – SP Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
20.6 Accessing 16-bit Timer/Counter Registers
11.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clk
CPU
, directly generated from the selected clock source for the chip. No internal
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
ATmega48PA/88PA/168PA
AVR CPU Core
© 2018 Microchip Technology Inc.
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