Datasheet

Figure 30-1. Addressing the Flash During SPM
PROGRAM MEMORY
0115
Z - REGISTER
BIT
0
ZPAGEMSB
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
INSTRUCTION WORD
PAGE
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAGE
PCWORDPCPAGE
PCMSB
PAGEMSB
PROGRAM
COUNTER
Note: The different variables used in this figure are listed in page size section in memory programming
chapter.
Related Links
32.6 Page Size
30.2.1 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses
and Lock bits from software will also be prevented during the EEPROM write operation. It is
recommended that the user checks the status of the EEPE bit in the EEPROM Control Register
(EECR.EEPE) and verifies that the bit is cleared before writing to the SPMCSR register.
30.2.2 Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits (LB) from software. To read the Lock bits, load the Z-
pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR (SPMCSR.BLBSET and
SPMCSR.SPMEN). When an LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN), the value of the Lock bits
will be loaded in the destination register. The SPMCSR.BLBSET and SPMCSR.SPMEN will auto-clear
upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When SPMCSR.BLBSET and SPMCSR.SPMEN
are cleared, LPM will work as described in the Instruction set Manual.
Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1
ATmega48PA/88PA/168PA
Self-Programming the Flash
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 339