Datasheet

26.9.5 TWI Control Register
Name: TWCR
Offset: 0xBC
Reset: 0x00
Property: -
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master
access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop
condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR.
It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.
Bit 7 6 5 4 3 2 1 0
TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE
Access
R/W R/W R/W R/W R/W R/W R R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – TWINT TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software
response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector.
While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by
software by writing a logic one to it.
Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also
note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register
(TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing
this flag.
Bit 6 – TWEA TWI Enable Acknowledge
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the
ACK pulse is generated on the TWI bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire serial bus
temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
Bit 5 – TWSTA TWI START Condition
The application writes the TWSTA bit to one when it desires to become a master on the 2-wire serial bus.
The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free.
However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a
new START condition to claim the bus master status. TWSTA must be cleared by software when the
START condition has been transmitted.
Bit 4 – TWSTO TWI STOP Condition
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire serial bus.
When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave
mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 306