Datasheet
Master SPI Mode: The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0
and UCPHA0 bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing for details.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
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Datasheet Complete
DS40002011A-page 263