Datasheet

22.11.8 Asynchronous Status Register
Name: ASSR
Offset: 0xB6
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB
Access
R/W R/W R R R R R
Reset 0 0 0 0 0 0 0
Bit 6 – EXCLK Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is
enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal.
Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal
oscillator will run only when this bit is zero.
Bit 5 – AS2 Asynchronous Timer/Counter2
When AS2 is written to zero, timer/counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to
one, timer/counter2 is clocked from a crystal oscillator connected to the timer oscillator 1 (TOSC1) pin.
When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A, and TCCR2B
might be corrupted.
Bit 4 – TCN2UB Timer/Counter2 Update Busy
When timer/counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2
has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in
this bit indicates that TCNT2 is ready to be updated with a new value.
Bit 3 – OCR2AUB Output Compare Register2A Update Busy
When timer/counter2 operates asynchronously and OCR2A is written, this bit becomes set. When
OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that OCR2A is ready to be updated with a new value.
Bit 2 – OCR2BUB Output Compare Register2B Update Busy
When timer/counter2 operates asynchronously and OCR2B is written, this bit becomes set. When
OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that OCR2B is ready to be updated with a new value.
Bit 1 – TCR2AUB Timer/Counter Control Register2 Update Busy
When timer/counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When
TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that TCCR2A is ready to be updated with a new value.
Bit 0 – TCR2BUB Timer/Counter Control Register2 Update Busy
When timer/counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When
TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical
zero in this bit indicates that TCCR2B is ready to be updated with a new value.
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 224