Datasheet

22.11.6 TC2 Interrupt Mask Register

Name: TIMSK2

Offset: 0x70

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

OCIE2B OCIE2A TOIE2

Access

R/W R/W R/W

Reset 0 0 0

Bit 2 – OCIE2B Timer/Counter 2, Output Compare B Match Interrupt Enable

When the OCIE2B bit is written to '1' and the I-bit in the Status register is set (one), the Timer/Counter2

Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in

Timer/Counter 2 occurs, i.e., when the OCF2B bit is set in 22.11.7 TIFR2.

Bit 1 – OCIE2A Timer/Counter 2, Output Compare A Match Interrupt Enable

When the OCIE2A bit is written to '1' and the I-bit in the Status register is set (one), the Timer/Counter2

Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in

Timer/Counter 2 occurs, i.e., when the OCF2A bit is set in 22.11.7 TIFR2.

Bit 0 – TOIE2 Timer/Counter 2, Overflow Interrupt Enable

When the TOIE2 bit is written to '1' and the I-bit in the Status register is set (one), the Timer/Counter2

Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter 2

occurs, i.e., when the TOV2 bit is set in 22.11.7 TIFR2.

ATmega48PA/88PA/168PA

8-bit Timer/Counter2 (TC2) with PWM and A...

Datasheet Complete

DS40002011A-page 222