Datasheet

The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase
correct PWM mode.
Table 22-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM2A[1] COM2A[0] Description
0 0 Normal port operation, OC2A disconnected.
0 1 WGM2[2 :0]: Normal port operation, OC2A disconnected.
WGM2[2:1]: Toggle OC2A on compare match.
1 0 Clear OC2A on compare match when up-counting. Set OC2A on compare
match when down-counting.
1 1 Set OC2A on compare match when up-counting. Clear OC2A on compare
match when down-counting.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. Refer to 22.7.4 Phase Correct PWM Mode for
details.
Bits 5:4 – COM2B[1:0] Compare Output Mode for Channel B
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B[1:0] bits are
set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to
enable the output driver.
When OC2B is connected to the pin, the function of the COM2B[1:0] bits depends on the WGM2[2:0] bit
setting. The table shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to a normal or
CTC mode (non- PWM).
Table 22-6. Compare Output Mode, Non-PWM
COM2B[1] COM2B[0] Description
0 0 Normal port operation, OC2B disconnected.
0 1 Toggle OC2B on compare match.
1 0 Clear OC2B on compare match.
1 1 Set OC2B on compare match.
The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM
mode.
Table 22-7. Compare Output Mode, Fast PWM
(1)
COM2B[1] COM2B[0] Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
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Datasheet Complete
DS40002011A-page 214