Datasheet

Table 20-2. Signal Description (Internal Signals)
Signal Name Description
Count Increment or decrement TCNT1 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT1 (set all bits to zero).
clk
T1
Timer/counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the
upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H
register can only be accessed indirectly by the CPU. When the CPU does an access to the TCNT1H I/O
location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated
with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register
value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within
one clock cycle via the 8-bit data bus.
Note: That there are special cases when writing to the TCNT1 register while the counter is counting will
give unpredictable results. These special cases are described in the sections where they are of
importance.
Depending on the selected mode of operation, the counter is cleared, incremented, or decremented at
each timer clock (clk
T1
). The clock clk
T1
can be generated from an external or internal clock source, as
selected by the clock select bits in the Timer/Counter1 Control Register B (TCCR1B.CS[2:0]). When no
clock source is selected (CS[2:0]=0x0) the timer is stopped. However, the TCNT1 value can be accessed
by the CPU, independent of whether clk
T1
is present or not. A CPU write overrides (i.e., has priority over)
all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation Mode bits in the Timer/
Counter Control Registers A and B (TCCR1B.WGM1[3:2] and TCCR1A.WGM1[1:0]). There are close
connections between how the counter behaves (counts) and how waveforms are generated on the
Output Compare outputs OC0x. For more details about advanced counting sequences and waveform
generation, see 20.12 Modes of Operation.
The timer/counter overflow flag in the TC1 Interrupt Flag Register (TIFR1.TOV) is set according to the
mode of operation selected by the WGM1[3:0] bits. TOV can be used for generating a CPU interrupt.
20.9 Input Capture Unit
The timer/counter1 incorporates an input capture unit that can capture external events and give them a
time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can
be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle and other features of the signal applied. Alternatively, the time-
stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram below. The elements of the block diagram that
are not directly a part of the input capture unit are gray shaded. The lower case “n” in register and bit
names indicates the timer/counter number.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 167