Datasheet

19.9.8 TC0 Interrupt Flag Register

Name: TIFR0

Offset: 0x35

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x15

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

OCF0B OCF0A TOV0

Access

R/W R/W R/W

Reset 0 0 0

Bit 2 – OCF0B Timer/Counter 0, Output Compare B Match Flag

The OCF0B bit is set when a compare match occurs between the Timer/Counter and the data in OCR0B

– Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit

in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/

Counter Compare Match Interrupt is executed.

Bit 1 – OCF0A Timer/Counter 0, Output Compare A Match Flag

The OCF0A bit is set when a compare match occurs between the Timer/Counter0 and the data in OCR0A

– Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG,

OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0

Compare Match Interrupt is executed.

Bit 0 – TOV0 Timer/Counter 0, Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic

one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are

set, the Timer/Counter 0 Overflow interrupt is executed.

The setting of this flag is dependent on the WGM0[2:0] bit setting. Refer to bit description of WGM0 in

TCCR0A.