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17.2.1 External Interrupt Control Register A
Name:  EICRA
Offset:  0x69
Reset:  0x00
Property:  -
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 7 6 5 4 3 2 1 0
ISC1[1:0] ISC0[1:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 3:2 – ISC1[1:0] Interrupt Sense Control 1
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT1 pin that activates the interrupt are
defined in the table below. The value on the INT1 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not recommended to generate an interrupt. If the low-level interrupt is selected, the low level
must be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00
The low level of INT1 generates an interrupt request.
01
Any logical change on INT1 generates an interrupt request.
10
The falling edge of INT1 generates an interrupt request.
11
The rising edge of INT1 generates an interrupt request.
Bits 1:0 – ISC0[1:0] Interrupt Sense Control 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT0 pin that activates the interrupt are
defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter
pulses are not recommended to generate an interrupt. If the low-level interrupt is selected, the low level
must be held until the completion of the currently executing instruction to generate an interrupt.
Value Description
00
The low level of INT0 generates an interrupt request.
01
Any logical change on INT0 generates an interrupt request.
10
The falling edge of INT0 generates an interrupt request.
11
The rising edge of INT0 generates an interrupt request.
ATmega48PA/88PA/168PA
EXTINT - External Interrupts
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 100