Datasheet

44
2545F–AVR–06/05
ATmega48/88/168
Figure 9-1. Reset Logic
Notes: 1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
9.0.3 Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 9-1. The POR is activated whenever V
CC
is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Table 9-1. Reset Characteristics
Symbol Parameter Min
(1)
Typ
(1)
Max
(1)
Units
V
POT
Power-on Reset Threshold Voltage (rising) 0.7 1.0 1.4 V
Power-on Reset Threshold Voltage (falling)
(2)
0.6 0.9 1.3 V
V
RST
RESET Pin Threshold Voltage 0.2 V
CC
0.9 V
CC
V
t
RST
Minimum pulse width on RESET Pin 2.5 µs
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RSTDISBL