Datasheet

349
2545F–AVR–06/05
ATmega48/88/168
5. Asynchronous Oscillator does not stop in Power-down
The Asynchronous oscillator does not stop when entering power down mode. This leads to
higher power consumption than expected.
Problem fix / Workaround
Manually disable the asynchronous timer before entering power down.
33.2 Errata ATmega88
The revision letter in this section refers to the revision of the ATmega88 device.
33.2.1 Rev. D
No errata.
33.2.2 Rev. B/C
Not sampled.
33.2.3 Rev. A
•
Writing to EEPROM does not work at low Operating Voltages
• Part may hang in reset
1. Writing to EEPROM does not work at low operating voltages
Writing to the EEPROM does not work at low voltages.
Problem Fix/Workaround
Do not write the EEPROM at voltages below 4.5 Volts.
This will be corrected in rev. B.
2. Part may hang in reset
Some parts may get stuck in a reset state when a reset signal is applied when the internal
reset state-machine is in a specific state. The internal reset state-machine is in this state for
approximately 10 ns immediately before the part wakes up after a reset, and in a 10 ns win-
dow when altering the system clock prescaler. The problem is most often seen during In-
System Programming of the device. There are theoretical possibilities of this happening also
in run-mode. The following three cases can trigger the device to get stuck in a reset-state:
- Two succeeding resets are applied where the second reset occurs in the 10ns window
before the device is out of the reset-state caused by the first reset.
- A reset is applied in a 10 ns window while the system clock prescaler value is updated by
software.
- Leaving SPI-programming mode generates an internal reset signal that can trigger this
case.
The two first cases can occur during normal operating mode, while the last case occurs only
during programming of the device.
Problem Fix/Workaround
The first case can be avoided during run-mode by ensuring that only one reset source is
active. If an external reset push button is used, the reset start-up time should be selected
such that the reset line is fully debounced during the start-up time.
The second case can be avoided by not using the system clock prescaler.