Datasheet

302
2545F–AVR–06/05
ATmega48/88/168
6. Values with “Power Reduction Register - PRR” enabled (0xFF).
27.3 External Clock Drive Waveforms
Figure 27-1. External Clock Drive Waveforms
27.4 External Clock Drive
Note: All DC Characteristics contained in this datasheet are based on simulation and characterization of
other AVR microcontrollers manufactured in the same process technology. These values are pre-
liminary values representing design targets, and will be updated after characterization of actual
silicon.
27.5 Maximum Speed vs. V
CC
Maximum frequency is dependent on V
CC.
As shown in Figure 27-2 and Figure 27-3, the Maxi-
mum Frequency vs. V
CC
curve is linear between 1.8V < V
CC
< 2.7V and between 2.7V < V
CC
<
4.5V.
V
IL1
V
IH1
Table 27-1. External Clock Drive
Symbol Parameter
V
CC
=1.8-5.5V V
CC
=2.7-5.5V V
CC
=4.5-5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/t
CLCL
Oscillator
Frequency
04010020MHz
t
CLCL
Clock Period 250 100 50 ns
t
CHCX
High Time 100 40 20 ns
t
CLCX
Low Time 100 40 20 ns
t
CLCH
Rise Time 2.0 1.6 0.5 µs
t
CHCL
Fall Time 2.0 1.6 0.5 µs
∆t
CLCL
Change in period
from one clock
cycle to the next
22 2%