Datasheet

95
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
Figure 14-1. 16-bit Timer/Counter Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 3, Table 10-3 on page 64 and Table 10-9 on page 69 for Timer/Counter1 pin
placement and description.
14.1.1 Registers
The Timer/Counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers.
Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the
Section 14.2 “Accessing 16-bit Registers” on page 96. The Timer/Counter control registers (TCCR1A/B) are 8-bit registers
and have no CPU access restrictions. Interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the
timer interrupt flag register (TIFR1). All interrupts are individually masked with the timer interrupt mask register (TIMSK1).
TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The clock select
logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clkT1).
Control Logic
TCNTn
Timer/Counter
Count
Clear
Direction
clk
Tn
OCRnA
OCRnB
ICRn
TCCRnA TCCRnB
=
Edge
Detector
(from Prescaler)
Clock Select
TOP BOTTOM
TOVn (Int. Req.)
OCnA (Int. Req.)
Tn
Waveform
Generation
Fixed
TOP
Value
DATA BUS
=
= = 0
OCnA
OCnB (Int. Req.)
Waveform
Generation
Noise
Canceler
OCnB
(From Analog
Comparator Output)
ICFn (Int. Req.)
Edge
Detector
ICPn