Datasheet

89
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
12.8.2 Timer/Counter Control Register B – TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating
in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the waveform
generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced
compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating
in PWM mode. When writing a logical one to the FOC0B bit, an immediate compare match is forced on the waveform
generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is
implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced
compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATmega48/88/168 and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the Section 12.8.1 “Timer/Counter Control Register A – TCCR0A” on page 87.
• Bits 2:0 – CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter.
Table 12-8. Waveform Generation Mode Bit Description
Mode WGM02 WGM01 WGM00
Timer/Counter
Mode of Operation TOP
Update of
OCRx at
TOV Flag
Set on
(1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –
5 1 0 1 PWM, phase correct OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
Bit 7 6 5 4 3 210
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0