Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
88
Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the output compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting.
Table 12-5 on page 88 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode
(non-PWM).
Table 12-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.
Table 12-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATmega48/88/168 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-8. Modes of
operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and
two types of pulse width modulation (PWM) modes (see Section 12.6 “Modes of Operation” on page 81).
Table 12-5. Compare Output Mode, non-PWM Mode
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on compare match
1 0 Clear OC0B on compare match
1 1 Set OC0B on compare match
Table 12-6. Compare Output Mode, Fast PWM Mode
(1)
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved
1 0 Clear OC0B on compare match, set OC0B at TOP
1 1 Set OC0B on compare match, clear OC0B at TOP
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 12.6.3 “Fast PWM Mode” on page 83 for more
details.
Table 12-7. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved
1 0
Clear OC0B on compare match when up-counting. Set OC0B on compare match when
down-counting.
1 1
Set OC0B on compare match when up-counting. Clear OC0B on compare match when
down-counting.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 12.6.4 “Phase Correct PWM Mode” on page 84 for
more details.