Datasheet
87
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
12.8 8-bit Timer/Counter Register Description
12.8.1 Timer/Counter Control Register A – TCCR0A
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the output compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 12-2
shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Table 12-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Table 12-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.
Bit 7 6 5 4 3 210
COM0A1 COM0A0 COM0B1 COM0B0 ––WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 12-2. Compare Output Mode, non-PWM Mode
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on compare match
1 0 Clear OC0A on compare match
1 1 Set OC0A on compare match
Table 12-3. Compare Output Mode, Fast PWM Mode
(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1
WGM02 = 0: normal port operation, OC0A disconnected.
WGM02 = 1: toggle OC0A on compare match.
1 0 Clear OC0A on compare match, set OC0A at TOP
1 1 Set OC0A on compare match, clear OC0A at TOP
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 12.6.3 “Fast PWM Mode” on page 83 for more
details.
Table 12-4. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1
WGM02 = 0: normal port operation, OC0A disconnected.
WGM02 = 1: toggle OC0A on compare match.
1 0
Clear OC0A on compare match when up-counting. Set OC0A on compare match
when down-counting.
1 1
Set OC0A on compare match when up-counting. Clear OC0A on compare match
when down-counting.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 14.8.4 “Phase Correct PWM Mode” on page 108 for
more details.