Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
66
Table 10-4 and Table 10-5 relate the alternate functions of port B to the overriding signals shown in Figure 10-5 on page 62.
SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and
SPI SLAVE INPUT.
Table 10-4. Overriding Signals for Alternate Functions in PB7..PB4
Signal Name PB7/XTAL2/TOSC2/PCINT7
(1)
PB6/XTAL1/TOSC1/PCINT6
(1)
PB5/SCK/PCINT5 PB4/MISO/PCINT4
PUOE INTRC × EXTCK+ AS2 INTRC + AS2 SPE × MSTR SPE × MSTR
PUOV 0 0 PORTB5 × PUD PORTB4 × PUD
DDOE INTRC × EXTCK+ AS2 INTRC + AS2 SPE × MSTR SPE × MSTR
DDOV 0 0 0 0
PVOE 0 0 SPE × MSTR SPE × MSTR
PVOV 0 0 SCK OUTPUT SPI SLAVE OUTPUT
DIEOE
INTRC × EXTCK + AS2 +
PCINT7 × PCIE0
INTRC + AS2 + PCINT6 ×
PCIE0
PCINT5 × PCIE0 PCINT4 × PCIE0
DIEOV (INTRC + EXTCK) × AS2 INTRC × AS2 1 1
DI PCINT7 INPUT PCINT6 INPUT
PCINT5 INPUT
SCK INPUT
PCINT4 INPUT
SPI MSTR INPUT
AIO Oscillator output Oscillator/clock input – –
Note: 1. INTRC means that one of the internal RC oscillators are selected (by the CKSEL fuses), EXTCK means that
external clock is selected (by the CKSEL fuses).
Table 10-5. Overriding Signals for Alternate Functions in PB3..PB0
Signal Name PB3/MOSI/OC2/PCINT3 PB2/SS/OC1B/PCINT2 PB1/OC1A/PCINT1 PB0/ICP1/PCINT0
PUOE SPE × MSTR SPE × MSTR 0 0
PUOV PORTB3 × PUD PORTB2 × PUD 0 0
DDOE SPE × MSTR SPE × MSTR 0 0
DDOV 0 0 0 0
PVOE
SPE × MSTR +
OC2A ENABLE
OC1B ENABLE OC1A ENABLE 0
PVOV
SPI MSTR OUTPUT +
OC2A
OC1B OC1A 0
DIEOE PCINT3 × PCIE0 PCINT2 × PCIE0 PCINT1 × PCIE0 PCINT0 × PCIE0
DIEOV 1 1 1 1
DI
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT SPI SS PCINT1 INPUT
PCINT0 INPUT
ICP1 INPUT
AIO – – – –