Datasheet

37
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
7.8.4 Internal Voltage Reference
The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC.
If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will
not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If
the reference is kept on in sleep mode, the output can be used immediately. Refer to
Section 8.8 “Internal Voltage Reference” on page 43 for details on the start-up time.
7.8.5 Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it
will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute
significantly to the total current consumption. Refer to Section 8.9 “Watchdog Timer” on page 44 for details on how to
configure the watchdog timer.
7.8.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure
that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O
) and the ADC clock (clk
ADC
) are stopped,
the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Section 10.2.5 “Digital Input Enable and Sleep Modes” on page 61 for details on which pins are enabled. If the input buffer is
enabled and the input signal is left floating or have an analog signal level close to V
CC
/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC
/2 on an input
pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input
disable registers (DIDR1 and DIDR0). Refer to Section 20.3.1 “Digital Input Disable Register 1 – DIDR1” on page 205 and
Section 21.6.5 “Digital Input Disable Register 0 – DIDR0” on page 220 for details.
7.8.7 On-chip Debug System
If the on-chip debug system is enabled by the DWEN fuse and the chip enters sleep mode, the main clock source is enabled
and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.