Datasheet

31
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
6.10 Timer/Counter Oscillator
The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a external clock source. The
Timer/Counter oscillator pins (TOSC1 and TOSC2) are shared with XTAL1 and XTAL2. This means that the Timer/Counter
oscillator can only be used when an internal RC oscillator is selected as system clock source. See Figure 6-2 on page 25 for
crystal connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR register written to logic one. See
Section 15.9 “Asynchronous operation of the Timer/Counter” on page 134 for further description on selecting external clock
as input instead of a 32kHz crystal.
6.11 System Clock Prescaler
The Atmel
®
ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by setting the
Section 6.11.1 “Clock Prescale Register – CLKPR” on page 31. This feature can be used to decrease the system clock
frequency and the power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and
clk
FLASH
are divided by a factor as shown in Table 8-1 on page 40.
When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system.
It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at
the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to
the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 × T2
before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock
period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
6.11.1 Clock Prescale Register – CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the
other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when
CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor
clear the CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input
to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are
given in Table 6-14 on page 32.
Bit 76543210
CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R/W R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description