Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
30
6.8 External Clock
The device can utilize a external clock source as shown in Figure 6-4. To run the device on an external clock, the CKSEL
fuses must be programmed as shown in Table 6-12.
Figure 6-4. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-13.
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable
operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable
behavior. If changes of more than 2% is required, ensure that the MCU is kept in reset during the changes.
Note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation. Refer to Section 6.11 “System Clock Prescaler” on page 31 for details.
6.9 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed.
This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during
reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the
internal RC oscillator, can be selected when the clock is output on CLKO. If the system clock prescaler is used, it is the
divided system clock that is output.
Table 6-12. Full Swing Crystal Oscillator operating modes
(2)
Frequency Range
(1)
(MHz) CKSEL3..0 Recommended Range for Capacitors C1 and C2 (pF)
0 - 100 0000 12 - 22
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. If 8MHz frequency exceeds the specification of the device (depends on V
CC
), the CKDIV8 fuse can be
programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock
meets the frequency specification of the device.
Table 6-13. Start-up Times for the External Clock Selection
Power Conditions
Start-up Time from Power-down and
Power-save Additional Delay from Reset (V
CC
= 5.0V) SUT1..0
BOD enabled 6CK 14CK 00
Fast rising power 6CK 14CK + 4.1ms 01
Slowly rising power 6CK 14CK + 65ms 10
Reserved 11
XTAL2
XTAL1
GND
NC
EXTERNAL
CLOCK
SIGNAL