Datasheet
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
290
0x39 (0x59) Reserved – – – – – – – –
0x38 (0x58) Reserved
– – – – – – – –
0x37 (0x57) SPMCSR SPMIE (RWWSB)
(5)
– (RWWSRE)
(5)
BLBSET PGWRT PGERS SELFPRGEN 233
0x36 (0x56) Reserved
– – – – – – – –
0x35 (0x55) MCUCR
– – –PUD– – IVSEL IVCE
0x34 (0x54) MCUSR
– – – – WDRF BORF EXTRF PORF
0x33 (0x53) SMCR
– – – – SM2 SM1 SM0 SE 33
0x32 (0x52) Reserved
– – – – – – – –
0x31 (0x51) Reserved
– – – – – – – –
0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 204
0x2F (0x4F) Reserved
– – – – – – – –
0x2E (0x4E) SPDR SPI Data Register 144
0x2D (0x4D) SPSR SPIF WCOL
– – – – – SPI2X 143
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 142
0x2B (0x4B) GPIOR2 General purpose I/O register 2 22
0x2A (0x4A) GPIOR1 General purpose I/O register 1 22
0x29 (0x49) Reserved
– – – – – – – –
0x28 (0x48) OCR0B Timer/Counter0 output compare register B
0x27 (0x47) OCR0A Timer/Counter0 output compare register A
0x26 (0x46) TCNT0 Timer/Counter0 (8-bit)
0x25 (0x45) TCCR0B FOC0A FOC0B
– – WGM02 CS02 CS01 CS00
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0
– –WGM01WGM00
0x23 (0x43) GTCCR TSM
– – – – – PSRASY PSRSYNC 93/137
0x22 (0x42) EEARH (EEPROM address register high byte)
(5)
17
0x21 (0x41) EEARL EEPROM address register low byte 17
0x20 (0x40) EEDR EEPROM data register 18
0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 18
0x1E (0x3E) GPIOR0 General purpose I/O register 0 22
0x1D (0x3D) EIMSK
– – – – – – INT1 INT0 74
0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 74
0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0
0x1A (0x3A) Reserved
– – – – – – – –
0x19 (0x39) Reserved
– – – – – – – –
0x18 (0x38) Reserved
– – – – – – – –
29. Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR
®
, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing
I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48/88/168 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for Atmel
®
ATmega88/168