Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
288
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved
– – – – – – – –
(0x99) Reserved
– – – – – – – –
(0x98) Reserved
– – – – – – – –
(0x97) Reserved
– – – – – – – –
(0x96) Reserved
– – – – – – – –
(0x95) Reserved
– – – – – – – –
(0x94) Reserved
– – – – – – – –
(0x93) Reserved
– – – – – – – –
(0x92) Reserved
– – – – – – – –
(0x91) Reserved
– – – – – – – –
(0x90) Reserved
– – – – – – – –
(0x8F) Reserved
– – – – – – – –
(0x8E) Reserved
– – – – – – – –
(0x8D) Reserved
– – – – – – – –
(0x8C) Reserved
– – – – – – – –
(0x8B) OCR1BH Timer/Counter1 - Output compare register B high byte 117
(0x8A) OCR1BL Timer/Counter1 - Output compare register B low byte 117
(0x89) OCR1AH Timer/Counter1 - Output compare register A high byte 117
(0x88) OCR1AL Timer/Counter1 - Output compare register A low byte 117
(0x87) ICR1H Timer/Counter1 - Input capture register high byte 117
(0x86) ICR1L Timer/Counter1 - Input capture register low byte 117
(0x85) TCNT1H Timer/Counter1 - Counter register high byte 116
(0x84) TCNT1L Timer/Counter1 - Counter register low byte 116
(0x83) Reserved
– – – – – – – –
(0x82) TCCR1C FOC1A FOC1B
– – – – – – 116
(0x81) TCCR1B ICNC1 ICES1
– WGM13 WGM12 CS12 CS11 CS10 115
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0
– –WGM11WGM10 113
(0x7F) DIDR1
– – – – – –AIN1DAIN0D 205
(0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 220
(0x7D) Reserved – – – – – – – –
(0x7C) ADMUX REFS1 REFS0 ADLAR
– MUX3 MUX2 MUX1 MUX0 217
(0x7B) ADCSRB
–ACME – – – ADTS2 ADTS1 ADTS0 220
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 218
29. Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR
®
, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing
I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48/88/168 is a complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for Atmel
®
ATmega88/168