Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
266
27. 2-wire Serial Interface Characteristics
Table 27-1 describes the requirements for devices connected to the 2-wire serial bus. The Atmel
®
ATmega48/88/168 2-wire
serial interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 27-1.
Table 27-1. 2-wire Serial Bus Requirements
Parameter Condition Symbol Min Max Unit
Input low-voltage
VIL
–0.5 0.3 V
CC
V
Input high-voltage
VIH
0.7 V
CC
V
CC
+ 0.5 V
Hysteresis of schmitt trigger inputs
Vhys
(1)
0.05 V
CC
(2)
– V
Output low-voltage 3mA sink current
VOL
(1)
0 0.4 V
Rise time for both SDA and SCL
tr
(1)
20 + 0.1C
b
(3)(2)
300 ns
Output fall time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(3)
tof
(1)
20 + 0.1C
b
(3)(2)
250 ns
Spikes suppressed by input filter
tSP
(1)
0 50
(2)
ns
Input current each I/O pin 0.1V
CC
< V
i
< 0.9V
CC
I
i
–10 10 µA
Capacitance for each I/O Pin C
i
(1)
– 10 pF
SCL clock frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
f
SCL
0 400 kHz
Value of pull-up resistor
f
SCL
≤ 100kHz
Rp
f
SCL
> 100kHz
Hold time (repeated) START Condition
f
SCL
≤ 100kHz
t
HD;STA
4.0 – µs
f
SCL
> 100kHz 0.6 – µs
Low period of the SCL clock
f
SCL
≤ 100kHz
(6)
t
LOW
4.7 – µs
f
SCL
> 100kHz
(7)
1.3 – µs
High period of the SCL clock
f
SCL
≤ 100kHz
t
HIGH
4.0 – µs
f
SCL
> 100kHz 0.6 – µs
Set-up time for a repeated START condition
f
SCL
≤ 100kHz
t
SU;STA
4.7 – µs
f
SCL
> 100kHz 0.6 – µs
Data hold time
f
SCL
≤ 100kHz
t
HD;DAT
0 3.45 µs
f
SCL
> 100kHz 0 0.9 µs
Data setup time
f
SCL
≤ 100kHz
t
SU;DAT
250 – ns
f
SCL
> 100kHz 100 – ns
Notes: 1. In Atmel ATmega48/88/168, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega48/88/168 2-wire serial interface operation. Other devices connected to the 2-
wire serial bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the Atmel ATmega48/88/168 2-wire serial interface is (1/f
SCL
– 2/f
CK
), thus f
CK
must
be greater than 6MHz for the low time requirement to be strictly met at f
SCL
= 100kHz.
7. The actual low period generated by the ATmega48/88/168 2-wire serial interface is (1/f
SCL
– 2/f
CK
), thus the low time
requirement will not be strictly met for f
SCL
> 308kHz when f
CK
= 8MHz. Still, ATmega48/88/168 devices connected to
the bus may communicate at full speed (400kHz) with other ATmega48/88/168 devices, as well as any other device
with a proper t
LOW
acceptance margin.
V
CC
0,4V–
3mA
----------------------------
1000ns
C
b
-----------------
Ω
V
CC
0,4V–
3mA
----------------------------
300ns
C
b
--------------
Ω