Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
256
25.8 Serial Downloading
Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.
The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET
is set low, the programming enable
instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-14 on page 247,
the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.
Figure 25-10. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. V
CC
– 0.3V < AV
CC
< V
CC
+ 0.3V, however, AV
CC
should always be within 1.8 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode
ONLY) and there is no need to first execute the chip erase instruction. The chip erase operation turns the content of every
memory location in both the program and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK)
input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
25.8.1 Serial Programming Algorithm
When writing serial data to the Atmel
®
ATmega48/88/168, data is clocked on the rising edge of SCK.
When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See Figure 25-11 on page 257
for timing details.
To program and verify the ATmega48/88/168 in the serial programming mode, the following sequence is recommended (See
four byte instruction formats in Table 25-17 on page 258):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the programmer can
not guarantee that SCK is held low during power-up. In this case, RESET
must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin
MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync.
the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. Whether
the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET
a positive pulse and issue a new programming enable command.
GND
XTAL1
RESET
VCC
AVCC
+ 2.7V to 5.5V
+ 2.7V to 5.5V
(2)
MOSI
MISO
SCK