Datasheet

255
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 25-7 on page 254 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to reading
operation.
Table 25-15. Parallel Programming Characteristics, V
CC
= 5V ±10%
Parameter Symbol Min Typ Max Unit
Programming enable voltage V
PP
11.5 12.5 V
Programming enable current I
PP
250 µA
Data and control valid before XTAL1 high t
DVXH
67 ns
XTAL1 low to XTAL1 high t
XLXH
200 ns
XTAL1 pulse width high t
XHXL
150 ns
Data and control hold after XTAL1 low t
XLDX
67 ns
XTAL1 low to WR low t
XLWL
0 ns
XTAL1 low to PAGEL high t
XLPH
0 ns
PAGEL low to XTAL1 high t
PLXH
150 ns
BS1 valid before PAGEL high t
BVPH
67 ns
PAGEL pulse width high t
PHPL
150 ns
BS1 hold after PAGEL low t
PLBX
67 ns
BS2/1 hold after WR low t
WLBX
67 ns
PAGEL low to WR low t
PLWL
67 ns
BS1 valid to WR low t
BVWL
67 ns
WR pulse width low t
WLWH
150 ns
WR low to RDY/BSY low t
WLRL
0 1 µs
WR low to RDY/BSY high
(1)
t
WLRH
3.7 4.5 ms
WR Low to RDY/BSY high for chip erase
(2)
t
WLRH_CE
7.5 9 ms
XTAL1 low to OE low t
XLOL
0 ns
BS1 valid to DATA valid t
BVDV
0 250 ns
OE low to DATA valid t
OLDV
250 ns
OE high to DATA tri-stated t
OHDZ
250 ns
Notes: 1. t
WLRH
is valid for the write flash, write EEPROM, write fuse bits and write lock bits commands.
2. t
WLRH_CE
is valid for the chip erase command.
XTAL1
BS1
OE
DATA
XA0
XA1
t
BVDV
t
XLOL
t
OLDV
t
OHDZ
Load Address
(Low Byte)
Read Data
(Low Byte)
Read Data
(High Byte)
Load Address
(Low Byte)
ADDR0 (Low Byte) ADDR1 (Low Byte)DATA (Low Byte) DATA (High Byte)